{[ promptMessage ]}

Bookmark it

{[ promptMessage ]}

old_mid_term_2008 - (15 points FPGA Programming...

Info iconThis preview shows pages 1–10. Sign up to view the full content.

View Full Document Right Arrow Icon
Background image of page 1

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 2
Background image of page 3

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 4
Background image of page 5

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 6
Background image of page 7

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 8
Background image of page 9

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full Document Right Arrow Icon
Background image of page 10
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: (15 points: FPGA Programming Technologies) 2. Answer the following questions. (4 points) (1). Divide the following storage devices into One-Time Programmable (OTP) and those that can be programmed multiple times. a. SRAM b. fusible-link c. antifuse d. FLASH W ' e. EPROM (OTP/ '"er ) 9/- (2 points) (2) A SRAM based programming technology element is larger than an antifuse. @/ False) a" [2/ . . . MWS (2 pomts) (3) A blown antifuse 1s... _ A. open-circuit @ resistive connection melted wire D. none of these 2, / . (2 points) (4) FLOTOX EEPROM cell has double polysilicon gates, with the top polysilicon as the floating gate and the lower polysilicon as the control 2- gate. (True/ als )V/ (2 points) (5) Programming technology that provides the best resistance against space radiation is: 2 1. SRAM 2. EEPROM @ Antifuse 4. EPROM (3 points) (6) Describe the advantage of a metal—metal antifuse over a poly— diffusion antifuse. fit 9. not WWW - rf\ (15 points: EEPROM 3. Apply correct voltages (15V, 5V, 0V) to BL, WL, and Control of the EEPROM cell shown below according to the following configurations. (5 points) (1) Precharge Floating Gate with Electrons (Programming the EEPROM cell) -4..— t» / BL WL ‘ AT : 2‘ l L I?) fil ‘ C) J 1 Control —5 35 ( ,_// (5 points) (2) Remove Electrons from Floating Gate (Programming the EEPROM cell) Control E—l 3 ! / —.. (5 points) (3) Reading the EEPROM cell (Also describe the output behavior when the floating gate is charged/uncharged with electrons.) (10 points: M UX-Based & LU T -Based Logic Blocks) 4. Demonstrate how the function f = w2w3’ + w1w3 + w2’w3 can be implemented using MUX— Based and LUT-Based Logic Blocks. (3 points) (1) LUT-Based 000 i 3 l °°‘ ‘ mo f UH \_. ,> r ,, 100 \/ | 01 v | no (7 points) (,2) Mux-Based (Show your derivation based on Shannon’s Expansion Theorem) . a I ‘ ' A. “j i 7 a; 4 ’ ‘ V w"). ' ,. ,_ ~~~~~~ -— ..i V) ./ - V (10 points: ASICs vs. PLDS) 1. Answer the following questions. (2 points) (1) Select all of the properties for Gate Array-Based ASle 1 Chip is partially fabricated 2. All mask layers for transistors and interconnect are customized. / my 3. Detailed design of logic cells, circuit, and layout is done by design ‘/ -» 1;) engineers. / 4 Reduced fabrication time. éi’Chip 1s built from pre- -defined modules called “standard cells”. (2 points) (2) Once an FPGA design is verified, Altera provides an option called “Hard Copy” to migrate the validated design to ( ). l. Full Custom ASIC 2. Gate Array—Based ASIC 2.! 3. Standard Cell— Based ASIC 4 Structured ASIC (2 points) (3) In Xilinx FPGA device, how many distributed SelectRams would be needed to implement a memory with 512 32-bit wide words? (Each distributed SelectRam is one 4-input LUT) 3,124,521 i" \(’~Z”V'\ / g7 16 > 2/ ./ (2 points) (4) As both LUT and cluster size increase, the critical path delay 1/; monotonically (increases (decreases) with diminishing returns. I / k (2 points) (5) What is one advantage and one disadvantage that designs using “FPGAs” have compared to designs using “Standard Cells”? 2 (10 points: Transistor Pairs) 5. The following figure shows the logic cell with fine granularity. Implement the Boolean function shown below by connecting the transistors together. If necessary, some nodes can be connected to Power and Ground. / ,x $3.. f=ab+~c a: (20 points: FPGA Architecture) 6. Please answer the following questions. (3 points) (1) Fill in the truth table for l-bit full adder implementation, and draw the logic gates (using AND, OR, XOR) inside the given module below. Cout Sum ( 7 points) (2) The following figure shows 4-bit adder which will be implemented by using the configurable logic block shown below. You will partition the logic circuits so that it can be implemented with as few CLBS as possible. Indicate your answer by filling in the table: one row per CLB used; write in the name of the signal wire from the logic circuit that corresponds to the CLB input or output; for the configuration bit, s, write in a “0” or “1”. If the required signal is not named in the diagram, label it. (Adder logic which is typically mapped to special purpose hardware is ignored in this problem.) HFHWHQ—Hi A3 B3 C3 A2 82 C2 A1 B1 A0 BO Cin i i Cout C3 ll_" “3i “i :i ”I Configurable Logic Block (I) 2 C2 81 C1 80 J (Configuration Bit) 5 f" F/F a *fi’ _ i a h b ~fia 3-LUT r—i c —r—>! l (10 points: FPGA Architecture) 8. Configure the following two logic blocks and interconnect them together to implement a Module-4 counter with the following specification. (Inputs: enable, clock, Outputs: count[l], count[0]) enable:1 enable=0 enable=0 enable:1 enable:1 enable:1 mux ' j flip-flop , v.5 , L‘ «c . \1 ,. L s (10 points: FPGA Logic Blocks) 7. Describe how many "Add Stages" are necessary to implement an adder for 128 N-bit numbers when Xilinx Virtex II or Altera Stratix ll FPGA devices are used. (Hint) The following figures show different implementations of a simple 3- input 2—bit adder based on their different architectures. -‘ L," l - l. l l . Au?) 8(0) Sumft); S'zmn'Ul (70} ‘y 3"? 1‘} Sunni} cm Cam Cf!) Snmii I Primal ("any C0713 4——+ 2 Add Stages 1 Add Stage l v I: ~~~~~ l J! , _, «a a a 4 ' \ ' ’-\ \ ‘ / \' j” g ., \ ,k\ ‘1, A '35 t\ ‘l l ’ j ,5! J 2 W ! a «l '\ i) N)" 3 26/ h (A Aim“ at z «a * -1 ‘33:” ~ \k - l l l) (C ““““ f" r ’; 5* 5?“ (‘l F x W ' a V V ‘ M w 3 z 7~ f“ z, 4 I l , 4/ I. l 7x l _ l 1 , 3% I J— ,J— -——-.—;~.’~ _~- my" " 1‘ l 1) f . ’ l b 7( l 1 x f, If)“ ‘, ' r / x" i // J I: \- ) l / '1 -. v5 l V, l ff‘ \ a, l‘ / \ [firfi-"w, \ 33f y, I / ;, I" V I “Ml l I") (7 points) (3) The following architecture shows the top half of Xilinx Virtex i’ w I L" 11 Slice. Demonstrate how this architecture can be configured to implement l-bit full adder with the contents of the LUT. SHlF'TiN ; u‘ ‘ com I V a SOF'IN — ’ I OH C‘e’ r. I YBMUX :34 . MEXCV‘ \ G3 —» f \ G? -, .7 1 G! I» %” I gym IX was: - ' .. t L a! '“" 'I W " — ' we: .- * . DFF ; ULMCH more - ’ mum: O Y , CE : . CK 1 SR HEV BY - ll ' I o. ‘ sucewgzzm was ant rout 5R - “@2101 ' WE = CLK I I l {:5 -- » ~ '~" I a ‘ Share between I CLK - . - "I my Beggars I SH n» I. - CIN (3 points) (4) How many slices are required to implement 4—bit adder? . 3090 UT -YB 77—h “'1 xx" :2: a DY...c -0 . DIG 35%?“ 'H i‘dffil“ w ”1“") r ., 6r" ‘ ‘ ...
View Full Document

{[ snackBarMessage ]}