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verilog - C.K Yang courtesy of M Horowitz and T Chanak...

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C.K. Yang M216A courtesy of M. Horowitz and T. Chanak Design of VLSI Circuits and Systems Verilog According to Tom 1 Verilog According to Tom 1.0 What’s Verilog? The name Verilog refers to both a language and a simulator which are used to functionally specify and model digital systems. This document describes Verilog in the context of producing RTL models of hardware, especially hardware which will subsequently be implemented. Hopefully this document along with some example Verilog code provide what most students need to master Verilog syntax, semantics, and good coding prac- tice, leaving the Verilog reference manuals to be reference manuals. 1.1 The Verilog Language Verilog HDL (Hardware Description Language) was concocted by Gateway Design Automation and later put in the public domain by Cadence Design Sys- tems in order to promote the language as a standard. Verilog models look like programs. Descriptions are partitioned into Verilog mod- ules . Modules resemble subroutines in that you can write one description and use (instantiate) it in multiple places. You can assemble modules hierarchically. Lower-level modules will have inputs and outputs which syntactically look like procedure parameters. The higher-level module instantiates them and connects their input and output ports with Verilog “wires” in a syntax that looks like a procedure call. The lowest modules in the hierarchy, and possibly others, will have descriptions of functionality. Both declarative and procedural descriptions look like C-language statements with C-like expression operators, but with different meaning for the “variables”. // Verilog Example, an SR-latch made from two nand gates // This description has no delays, so it won’t actually work, // but it shows how modules are put together. module nand(in1, in2, out); input in1, in2; output out; assign out = ~(in1 & in2); endmodule
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C.K. Yang M216A courtesy of M. Horowitz and T. Chanak Design of VLSI Circuits and Systems Verilog According to Tom 2 // This module instantiates and “hooks up” two “nand” modules module srlatch(s, r, q, q_b); input s,r; output q, q_b; nand nand1(s, q_b, q); nand nand2(r, q, q_b); endmodule 1.2 The Verilog Simulator Cadence Design Systems sells Verilog-XL , a simulator for the Verilog HDL lan- guage. Verilog-XL compiles and runs a system’s modules either interactively or in batch mode. Special waveform and state displays are available. Section 5.0 con- tains details and hints for running Verilog - XL . If the simulated system spans several files, Verilog-XL can assemble it regardless of the order the files are specified in. Verilog-XL compiles the entire system on each invocation, so there are no intermediate “object” files nor is there an explicit link phase. The compilation step is quite fast, not at all in the way of getting things done.
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