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Unformatted text preview: Practices”, 4rth Edition Updated, Prentice-Hall International, 2007. Tutorials 12 tutorial sessions starting from Week 2. Problem set on IVLE course web page. Will assign problems after lecture for following week’s tutorial. Laboratory Held in Digital Electronics Lab (E4-03-07) See ECE timetable for schedule Before starting labs, view the lab video at http://www.ee.nus.edu.sg/~eledigit/modules/ee20 06/ee2006wc.htm (Link from Course IVLE page -> circuit ideas page -> video presentation on circuit design) Assessment Mid-term 20% D1 Design Lab 25% D2 VHDL Lab Test 15% Final Exam 40% No calculators allowed in any Exam! Pre-requisite Material From EG1108 or equivalent Basic gates: AND, OR, NOT, NAND, NOR, EX-OR SOP and POS expressions from Truth Tables Boolean Identities De Morgan’s Laws Simplifying Boolean Expressions....
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- Spring '11
- Logic gate, Akash kumar, STATE MACHINE DESIGN