Topic 5 Combinational Logic

Topic 5 Combinational Logic - Outline Outline Topic 5 g...

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Topic 5 Combinational Logic Circuits g (MSI Elements) Akash Kumar utline Outline Introduction Binary adders Half adders, full adders, ripple adders. Magnitude comparators Decoders, BCD to 7-segment decoders ncoders, Priority encoders Encoders, Priority encoders Multiplexers ri tate logic elements Tri-state logic elements Demultiplexers Akash Kumar EE2006 2 SI Elements MSI Elements Introduce a higher level of functionality in digital design compared to ‘low level’ gate-based design e.g. C programming vs. assembly programming. Two main types yp Combinational utputs dependent only on current input 1 7 3 Outputs dependent only on current input Sequential utputs dependent on both ast nd present Outputs dependent on both past and present inputs plies they must have memory Implies they must have memory Akash Kumar EE2006 3 INARY ADDERS BINARY ADDERS Akash Kumar EE2006 4
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alf Adders Half Adders Need to add bits {0,1} of A i and B i Associate 10 : ni i A AA A A  1 i C binary bit 0 logic value F (0) inary bit 1 logic value T (1) : i BB BB B S binary bit 1 This leads to the following truth table i A i B i Sum i Carry i+1 00 0 0 ii i SUM AB A B A B  01 1 0 1 0 i i i B A CARRY 1 Akash Kumar EE2006 5 1 1 0 1 alf Adder Circuit Half Adder Circuit i SUM A B A B i i i B A CARRY 1 Akash Kumar EE2006 6 alf Adder Limitations Half Adder Limitations Half adder circuits do not suffice for general addition because they do not include the carry bit from the previous stage of addition, e.g. Carry 0 1 1 0 A 0 1 1 0 011 B + 0 0 1 1 SUM 1 0 0 1 Akash Kumar EE2006 7 ull Adders Full Adders Full adders can use the carry bit from the previous stage of addition A i B i C i S i C i+1 000 0 0 0 0 1 1 0 010 1 0 0 1 100 1 0 101 0 1 110 0 1 111 1 1 Akash Kumar EE2006 8
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ull Adders Full Adders A i B i C i 01 0 A i B i C i 0 Note: C i+1 is not a MSOP, but less overall hardware is reqd. if we use this expr. It 00 0 1 01 10 11 00 0 0 01 allows sharing of A i XOR B i between SUM i and C i+1 . 10 10 iii i ii i ii SUM ABC ABC A (B C B C ) A (B C B C )    ) ( i i i i i i i i i i i i i i i 1 i B A B A C B A C B A C B A B A C i i A(B C) A(B C)    ) ( i i i i i B A C B A Akash Kumar EE2006 9 ull Adder Circuit Full Adder Circuit ) ( 1 i i i i i i B A C B A C i i i C B A SUM ) ( Note: A full adder adds 3 bits. Can also consider as rst adding first two and then the result with the carry Akash Kumar EE2006 10 first adding first two and then the result with the carry arallel Adders Parallel Adders C 4 C 3 C 2 C 1 A 3 A 2 A 1 A 0 B 3 B 2 B 1 B 0 Akash Kumar EE2006 11 arallel Adders Parallel Adders 4 FA’s cascaded to form a 4-bit adder In general, N FA’s can be used to form a N -bit adder arry bits have to propagate from one stage to Carry bits have to propagate from one stage to the next. Inherent propagation delays associated ith this with this
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Topic 5 Combinational Logic - Outline Outline Topic 5 g...

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