EE1003_Chap3_Sem1_AY2011-12

EE1003_Chap3_Sem1_AY2011-12 - Chapter 3 Bit & Frame...

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Chapter 3 1 Bit Synchronization Let T b be the bit duration of a binary PCM waveform. Given a signaling rate of nf 0 bits per second, it follows that T b = 1 / ( nf 0 ) . Suppose that the PCM transmitter employs on-off keying (OOK) for transmission whereby bit 1 is represented as an “on” pulse and bit 0 is represented as an “off” pulse. Assuming that rectangular pulses are used, the PCM trans- mitter thus sends the bit sequence 1 , 0 , 1 , 0 , 1 , 0 , 1 , 0 ,... as the following OOK signal. Further assuming that the received pulses are still rectangu- lar, the receiver will make decisions at the midpoint of each pulse, as the midpoint is furthest from the boundaries of ad- jacent pulses. 1
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A clock is needed to time the decisions to be made. A clock is a periodic signal that is responsible for timing various events in a circuit. The clock that we desire is a rectangular pulse train of period T b . Thus, this clock is referred to as the bit clock . The receiver will make decisions at each rising edge of the bit clock. How do we ensure that the rising edges of the bit clock co- incide with the midpoints of the received pulses? Suppose we derive a rectangular pulse train of period 2 T b from the bit clock. We shall refer to this periodic signal as the local clock at the receiver. The local clock and received OOK signal must have a phase difference of π/ 2 . 2
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A device that derives the bit clock from the received OOK signal, and adjusts the phase of the bit clock until the de- sired phase difference of π/ 2 is achieved, is the digital phase- locked loop (DPLL). When the latter has been achieved, we say that the receiver is bit synchronized to the received OOK signal. 2 The DPLL A particular realization of a DPLL is shown below. 3
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The phase detector is an Exclusive-OR (XOR) gate. When used in the DPLL, one input will be the received OOK signal. The other input will be the local clock. Given the received OOK signal and local clock, the output of the phase detector changes depending on the phase difference between the two input signals. The K counter consists of an up-counter and a down- counter .A 1 /T m Hz input clock times the counting process of the two counters. This clock is typically a high-speed clock, many times faster than the signaling rate 1 /T b of the PCM system. 4
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EE1003_Chap3_Sem1_AY2011-12 - Chapter 3 Bit & Frame...

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