spaper01 - DESIGN AND IMPLEMENTATION OF A MULTITHREADED...

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DESIGN AND IMPLEMENTATION OF A MULTITHREADED HIGH RESOLUTION MPEG4 DECODER ON SANDBLASTER DSP Vaidyanathan Ramadurai, Sanjay Jinturkar, Mayan Moudgill, John Glossner Sandbridge Technologies, 1 North Lexington Avenue, White Plains, NY 10601 vramadurai@sandbridgetech.com ABSTRACT In this paper, we describe the design, implementation and multithreading of a MPEG 4 decoder (simple profile) for high resolution (VGA 640x480) on Sandblaster DSP. The implementation is done entirely in C. Software solution provides high reusability, low cost and short development time when compared to dedicated hardware solutions. We describe the multithreading of time critical tasks that are processor intensive as well as memory intensive. 1. INTRODUCTION MPEG4 is a multimedia standard adopted by the Moving Pictures Experts Group (MPEG) [1]. A simple profile MPEG4 decoder is defined by the standard for low complexity coding and decoding of rectangular video frames. Implementing an MPEG4 decoder on embedded processors has always been a challenging task. The computational and memory requirements for decoding high resolution video streams like VGA are demanding and require substantial optimizations. In this paper, we present the implementation of a simple profile MPEG4 decoder on Sandblaster DSP for high resolution VGA encoded video streams. We focus on multithreading and efficient handling of video frames using Direct Memory Access (DMA). We also describe the partitioning of various blocks in the decoder across multiple threads based on their computational and memory complexity. By exploiting these techniques, we achieve real time requirements. This paper is organized as follows. In Section 2, we provide an overview of a simple profile MPEG4 decoder. In Section 3, we discuss the Sandblaster multithreaded processor. In Section 4, we describe the multithreading of MPEG4 decoder for high resolution VGA streams. Section 5 concludes this paper. 2. SIMPLE PROFILE MPEG4 DECODER The block diagram of an MPEG4 decoder is shown in Fig. 1. A typical MPEG4 decoder unit consists of a Variable Length Decoder (VLD), Inverse Scanning, an Inverse AC/DC prediction, Inverse Quantizer and Inverse Transform (IDCT). In case of an inter coded block/frame, it is motion compensated before being sent to output. The reconstructed output frame is available in YUV format to be displayed. This procedure is applied for every macroblock and thus for every frame. Fig 1: MPEG4 Decoder Block The encoded data stream is demarcated into frames using start codes and end codes. Every frame is then subdivided into smaller units called macroblocks. Each macroblock is a set of 4 8x8 units of luminance (intensity) data and 2 8x8 units of chrominance (color) data. This subdivision facilitates processing the video data in smaller units rather than as an entire frame.
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spaper01 - DESIGN AND IMPLEMENTATION OF A MULTITHREADED...

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