646s05hw9 - D = 10 15 cm-3 The thickness of the gate oxide...

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ELEG 646; ELEG 446 - Nanoelectronic Device Principles – Spring 2005 Homework #9 - due Thursday, 12 May 2005, in class 1. An n-channel JFET is being used as a controlled load by operating the transistor in saturation. The pinch-off voltage of the transistor is 3.5 V; and the built-in voltage of the gate-channel junction is 0.8 V. The gate is grounded. Assume G O = 1.44x 10 -2 A/V and determine(a) the drain voltage V Dsat , (b) the value of the load resistor with V D = V Dsat , and (c) the g m of the JFET transistor in the saturation region. Compare the value of g m with that of a bipolar transistor with I C = I Dsat . 2. Starting from Eq. (4.5.6) and following the procedure described in the text, derive Eq. (4.5.9). 3. An n-type silicon sample has a uniform donor concentration N D = 5 x 10 15 cm -3 . Calculate the surface potential required (a) to make the surface intrinsic, and (b) to bring strong inversion at the surface. 4. An Au gate MOS capacitor is fabricated on an n-silicon substrate with N
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Unformatted text preview: D = 10 15 cm-3 . The thickness of the gate oxide is 120 nm, and the charge density at the Si-SiO 2 interface is 3 x 10 11 charges cm-2 . Calculate (a) the flat-band voltage, (b) the threshold voltage, and (c) draw the energy band diagram of the system under thermal equilibrium and at the onset of strong inversion. 5. Consider a MOS capacitor of area 1 cm 2 made on n-silicon with N D = 1.5 x 10 14 cm-3 and an Al gate. The SiO 2 layer is 200 nm thick. The Si is 20 µ m thick and is epitaxially grown on n +-silicon substrate having N D = 10 19 cm-3 . Neglecting any interface charge between Si and SiO 2 , determine the flat-band capacitance, and C max for the structure, and sketch the C-V plot. Homework assignments will appear on the web at: http://www.ece.udel.edu/~kolodzey/courses/eleg646s05.html Note: On each homework and report submission, you must please give your name, the due date, assignment number and the course number....
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