Appendix_A - Appendix A: Basic Pipelining: Basic and...

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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-1 Appendix A. Pipelining: Basic and Intermediate Concept What is Pipelining? Pipelining is an implementation technique whereby multiple instructions are overlaped in execution. Pipe stage (pipe segment) Throughput Machine cycle: The time required between moving an instruction one step down the pipeline. This time is equal to the time required for the slowest pipe stage. In a computer, the machine cycle is usually one clock cycle. The pipeline designer‘s goal is to balance the length of each pipe stage. If the stages are perfectly balanced, stages pipe of Number machine d unpipeline on n instructio per Time n instructio per Time =
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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-2 A Simple Implementation of A RISC ISA Five-cycle implementation Instruction fetch cycle (IF) Instruction decode/register fetch cycle (ID) Operand fetches; Sign-extending the immediate field; Decoding is done in parallel with reading registers. This technique is known as fixed-field decoding; Test branch condition and computed branch address; finished branching at the end of this cycle. Execution/effective address cycle (EX) Memory reference; Register-Register ALU instruction; Register-Immediate ALU instruction; Memory access/branch completion cycle (MEM) Write-back cycle (WB) Register-Register ALU instruction; Register-Immediate ALU instruction; Load instruction;
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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-3 Performance of the Five-Cycle Implementation CPI=4.54 Branch instructions (12%) take 2 cycles Store instructions (10%) require 4 cycles Others takes 5 cycles
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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-4 The Classic Five-Stage Pipeline for a RSIC Processor
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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-5 The RISC Pipeline with Registers
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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-6 Instruction Issue The process of letting an instruction move from the instruction decode stage (ID) into execution stage (EX) of this pipeline.
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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-7 Basic Performance Issues in Pipelining Pipelining increasing instruction execution throughput, but it does not reduce the execution time of an individual instruction due to pipeline overhead. Register delay Clock skew The limitation of pipeline depth is due to Pipeline latency Pipe stage imbalance Pipeline overhead Example in A-10.
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Rung-Bin Lin Appendix A: Basic Pipelining: Basic and Intermediate Concepts Appendix-8 The Major Hurdle of Pipelining - Pipelining Hazards A hazard is a situation that prevents the next instruction in the instruction stream from executing during its designated
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Appendix_A - Appendix A: Basic Pipelining: Basic and...

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