ass67 - Ch6 bus L1 bus master buffer cache cache swap...

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Ch6 bus L1 bus master buffer cache cache swap control bus clock stack pointer supervisor machine state interrupt handler stack interrupt bus arbitration unit memory bus I/O wait state address,control, data push pop ratio lossy, lossless cache controller I/o port control bus address bus linear address space logical accesses DMA channel cache hit bus protocol multicore scaling up multiple-processor storage 1.The system bus is the communication channel that connects all computer components. It physically consists of parallel transmission lines that can be grouped into those carrying memory addresses (the address bus), those carrying control and status signals (the control bus), and those carrying data (the data bus). In a logical sense, the bus also consists of the bus protocol. 2.A bus master is any device that can initiate a transfer across the bus. Allowing devices other than the CPU to be bus masters frees CPU cycles to perform other tasks. It also allows a form of parallelism in which peripheral-to-peripheral data transfers can occur simultaneously with instruction execution.
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3.The width of the data bus should equal or exceed CPU word size. The bus clock rate should match the CPU clock rate, though this is difficult or impossible to achieve. 4.An interrupt is a signal to the OS that a request or event has occurred that requires its attention. Interrupts are numeric codes and can be generated by peripheral devices, an explicit software instruction, or the CPU. Peripheral device interrupts are sent over the system bus, detected by the CPU, and placed in an interrupt register. Software and CPU-generated interrupts are placed in the interrupt register by the CPU. The CPU detects an interrupt by checking the interrupt register’s contents after each execution cycle. If an interrupt is present, the CPU suspends the current program by performing a push operation. It then branches to the supervisor, which looks up the interrupt code in a table and calls the interrupt handler address it finds there. When the interrupt handler returns to the supervisor, a pop operation is performed, which activates the program that was running when the interrupt was detected. 5.The stack is an area of memory that holds register values of suspended processes. It’s needed because register values represent a suspended program’s state. These values must be restored to CPU registers to allow a program to resume execution at the point it was suspended. Multiple sets of register values must be stored when interrupts of higher priority cause lower-priority interrupt handlers to be suspended and placed on the stack. 6.A push operation copies register values to the top of the stack and increments a pointer (called the stack register) to point to the new stack top. A pop operation removes stack contents on a last in, first out (LIFO) basis. Each pop operation decrements the stack pointer and copies one set of register values from the top of the stack to CPU registers. The last register value copied is
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This note was uploaded on 12/04/2011 for the course ACCT 200 taught by Professor Forny during the Spring '11 term at Art Inst. Phoenix.

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ass67 - Ch6 bus L1 bus master buffer cache cache swap...

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