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Homework6_Solution

# Homework6_Solution - Assignment#6 Digital Logic Design II...

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Assignment #6 – Digital Logic Design II – Sequential Logic CDA 3100, Computer Organization I  Problem 1 (50 points) Design a circuit that has an input clk, and an output Q which has three bits. At the rising edge of the clk, the unsigned binary number represented by Q changes according to the pattern: 04725631047256310…In other words, it starts with 0 and repeats 04725631 every 8 clock cycles. (a) (10 points) Write down the next-state table. Q2 Q1 Q0 D2 D1 D0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 1 0 0 1 1 0 0 1 1 1 1 0 1 1 1 0 1 1 0 0 1 1 1 1 1 0 1 0 (b) (10 points) Use Karnaugh map, derive the function for D2, D1, and D0. D2 = (~Q2&~Q0) | (Q2&~Q1) Q2Q 1 Q0 00 01 11 10 0 1 1 1 1 1 D1 = Q2

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Q2Q 1 Q0 00 01 11 10 0 1 1 1 1 1 D0 = (~Q2&Q1) | (Q2&~Q0) Q2Q 1 Q0 00 01 11 10 0 1 1 1 1 1 (c) (10 points) Write down a Verilog module for this circuit. Use the following code as a template. module HW6P1 (clk, Q); input clk; output [2:0] Q; wire Q2, Q2bar, Q1, Q1bar, Q0, Q0bar, D2, D1, D0; assign D0 = (~Q2&Q1) | (Q2&~Q0) ;
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Homework6_Solution - Assignment#6 Digital Logic Design II...

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