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Unformatted text preview: Problem 2 The following is the state diagram for a circuit that has two inputs, clk and X, and four states. Similar to the previous question, X may change every clock cycle, and the change happens at the falling edge of the clock. The circuit samples the input at every rising edge of the clock. If the input is 1, consider as read a 1, else read a 0. Assume that the circuit started in state S0. Please write in the figure to indicate the change of the state according to the input. S0 S1 S1 S2 S3 S2 S3 S1 S0 S1 S2 S3 X=1 X=0 X=1 X=0 X=1 X=0 X=1 X=0...
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- Spring '09
- Human mitochondrial DNA haplogroup, S6, digital SLR cameras