cpe323msp430_sysarch(1) - CPE 323 Introduction to Embedded...

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CPE 323 Introduction to Embedded Computer Systems: The MSP430 System Architecture Instructor: Dr Aleksandar Milenkovic Lecture Notes
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CPE 323 2 Outline MSP430: System Architecture ± System Resets, Interrupts, and Operating Modes ± Basic Clock Module ± Watchdog Timer
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MSP430: System Resets, Interrupts, and Operating Modes
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CPE 323 4 System Reset ± Power-on Reset (POR) ± Powering up the device ± A low signal on the RST/NMI pin when configured in the reset mode ± An SVS low condition when PORON=1. ± Power-up Clear ± A POR signal ± Watchdog timer expiration when in watchdog mode only ± Watchdog timer security key violation ± A Flash memory security key violation
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CPE 323 5 Power-On Reset (POR)
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CPE 323 6 Brownout Reset
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CPE 323 7 Device conditions after system reset ± The RST/NMI pin is configured in the reset mode ± I/O pins are switched to input mode as described in the Digital I/O chapter ± Other peripheral modules and registers are initialized as described in their respective chapters in this manual ± Status register (SR) is reset ± The watchdog timer powers up active in watchdog mode ± Program counter (PC) is loaded with address contained at reset vector location (0FFFEh). CPU execution begins at that address
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CPE 323 8 Software initialization Your SW must initialize the MSP430 ± Initialize the SP, typically to the top of RAM ± Initialize the watchdog to the requirements of the application ± Configure peripheral modules to the requirements of the application ± Additionally, the watchdog timer, oscillator fault, and flash memory flags can be evaluated to determine the source of the reset
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CPE 323 9 Interrupts ± 3 types ± System reset ± (Non)- maskable NMI ± Maskable ± Interrupt priorities are fixed and defined by the arrangement of modules
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CPE 323 10 (Non)-Maskable Interrupts (NMI) ± Sources ± An edge on the RST/NMI pin when configured in NMI mode ± An oscillator fault occurs ± An access violation to the flash memory ± Are not masked by GIE (General Interrupt Enable), but are enabled by individual interrupt enable bits (NMIIE, OFIE, ACCVIE)
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CPE 323 11 NMI Interrupt Handler
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CPE 323 12 Maskable Interrupts ± Caused by peripherals with interrupt capability ± Each can be disabled individually by an interrupt enable bit ± All can be disabled by GIE bit in the status register
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CPE 323 13 Interrupt acceptance ± 1) Any currently executing instruction is completed. ± 2) The PC, which points to the next instruction, is pushed onto the stack. ± 3) The SR is pushed onto the stack. ± 4) The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service. ± 5) The interrupt request flag resets automatically on single-source flags. Multiple source flags remain set for servicing by software.
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cpe323msp430_sysarch(1) - CPE 323 Introduction to Embedded...

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