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Unformatted text preview: Consulting & Engineering Services www.tanner.com/ces CES-mAMIs05DL Tanner Consulting & Engineering Services Presenting MAMIS035DL Digital Low Power Standard Cell Library For Mosis AMI 0.5µ Sub-micron Process Revision A mAMIs 0.5µ Consulting & Engineering Services www.tanner.com/ces CE-LI-PR-CE TANNER CES GENERAL TERMS & CONDITIONS Liability All designs will be implemented under the Client’s front-end specification. Our contracted engineering services are accomplished for the Client on a best effort basis. Quality assurance is achieved by arriving at a common understanding of the nature of the Project among the engineers and managers at the Client operation and at Tanner CES. Tanner Research is not liable for the functionality, quality, or performance of the Client’s future Projects using components produced as part of the contracted work. Tanner Research is not liable if the Client chooses to use our recommended design or application methodologies. If prototype chips are delivered, the process vendors do not generally guarantee yield, quality, or performance of their products. Neither does Tanner Research extend any warrantee to the contracted design and its fabricated results. Non-Disclosure Agreement Non-disclosure agreements (NDAs) serve the following purposes. o Signed between the Client and Tanner Research, the NDA protects Client’s original concept, status, and intentions in current and future product development and manufacturing. o Signed between the Client and Tanner Research, the NDA protects Tanner Research’ specific technologies, IC libraries, building blocks and methodologies that are developed prior to the Client Project, or developed specifically for the Client application. o Specific non-disclosure or non-distribution conditions may be added to the Statement of Work for individual Client Projects. These conditions do not replace or supercede any previously signed NDA; rather they serve as additional constraints to the NDA. o During or at the end of the Client Project, if we communicate with a process vendor or receive fabricated parts from a process vendor which will be forwarded to the Client, we assume that the Client is also a current customer of the vendor. We may request Client to provide a proof of its NDA with the vendor before any such communication or transaction. Ownership of Work Results The Client owns the delivered version and the fabricated version of the work results from a contracted Client Project. These results are subject to the following re-distribution conditions: o The Client agrees to use the work results only in its own Projects or products, as developed by the Client and on the Client’s own site. o The Client will not distribute copies of the delivered data files and documents (such as design, libraries, process technology setups, design flows and methodologies, software utilities, etc.) to any third parties or to any other Client site, with the following two exceptions: Exception 1: If applicable, results can be delivered to the Government Agency sponsoring the Client Project, if such delivery is negotiated as part of the Client Project. During contract negotiations, the Client shall inform Tanner Research about such a delivery and receive advance agreement from us for the contents to be disclosed. Exception 2: If applicable, results can be incorporated into published academic research or presented for academic purposes. During contract negotiation, the Client shall inform Tanner Research about such a presentation and receive advanced agreement from us for the contents to be disclosed. Any other exceptions shall be specified in a written document signed by both the Client and Tanner Research. Tanner Research does not own the original design and application concepts from the Client. We agree not to disclose the Client’s proprietary design and applications information. However, we shall distinguish the following items that remain the property of Tanner Research: o T he methodology used through the development of the Client Project, or that we planned for Client to apply the Project’s results, are usually either common knowledge in the industry or specific methods invented by Tanner Research. Using or adopting these methodologies in the Client Project does not institute the Client’s ownership to these methodologies. o Client does not own Tanner Research’s general-purpose building elements (such as cell libraries, building blocks, IO pad cells, etc.) that we utilize in a contracted Project. These building elements are Tanner Research’s current design resources that are widely used internally and/or distributed as commercial products. Using these building elements does not institute the Client’s ownership of them. Protect Tanner Research’s Engineering Resources Through the entire Client Project cycle, starting from bid and proposal to the end of the Project, the Client will contact various engineering resources within Tanner Research. These resources may include Tanner Research’s employees and its associates (subcontracting firms or individuals). The Client agrees not to recruit or hire any of these individuals or contract with any firms during the three years following Project completion. oþ Consulting & Engineering Services www.tanner.com/ces CES-mAMIs05DL Table of Contents 2x2 Input AND-OR Gate: ...................................................................................... AO22 2x2 Input AND-NOR Gate: ....................................................................................AOI22 1X-Drive Non-Inverting Buffer: ............................................................................ BUF1 4X-Drive Non-Inverting Buffer: ............................................................................ BUF4 Buffer Clock Left: ..........................................................................................BUFCLKL Buffer Clock Right: ....................................................................................... BUFCLKR 4X-Drive Inverter: ................................................................................................. BUFI4 Buffer Reset Left: ........................................................................................... BUFRSTL Buffer Reset Right:.........................................................................................BUFRSTR Tri-State Inverter: .................................................................................................. BUFZ Bus Clock Left: ...............................................................................................BUSCLKL Bus Clock Right:............................................................................................ BUSCLKR Bus Reset Left: ...............................................................................................BUSRSTL Bus Reset Right:............................................................................................ BUSRSTR D Flip-Flop: .......................................................................................................... DFF_S D Flip-Flop With Asynchronous Clear: ............................................................DFFC_S D Flip-Flop With Preset:.................................................................................... DFFP_S D Flip-Flop With Preset & Asynchronous Clear: ......................................... DFFPC_S Inverter: ...................................................................................................................... INV Dual Inverter:............................................................................................................ INV2 Tri-State Inverter:.....................................................................................................INVZ Latch:.........................................................................................................................LAT Latch With Clear: ................................................................................................... LATC Latch With Preset: ................................................................................................. LATP Latch With Preset & Clear:..................................................................................LATPC 2-Input Multiplexer:................................................................................................ MUX2 2-Input NAND Gate: .............................................................................................NAND2 2-Input NAND Gate With Complementary Output:......................................... NAND2C 3-Input NAND Gate: .............................................................................................NAND3 3-Input NAND Gate With Complementary Output:......................................... NAND3C Tanner Research, Inc. Consulting & Engineering Services www.tanner.com/ces CES-mAMIs05DL 4-Input NAND Gate: .............................................................................................NAND4 4-Input NAND Gate With Complementary Output:......................................... NAND4C 2-Input NOR Gate: .................................................................................................NOR2 2-Input NOR Gate With Complementary Output: ............................................. NOR2C 3-Input NOR Gate: .................................................................................................NOR3 3-Input NOR Gate With Complementary Output: ............................................. NOR3C 4-Input NOR Gate: .................................................................................................NOR4 4-Input NOR Gate With Complementary Output: ............................................. NOR4C Schmitt Trigger Inverter:.........................................................................................SINV 2-Input Exclusive-NOR Gate:............................................................................. XNOR2 2-Input Exclusive-OR Gate: .................................................................................. XOR2 Buffer Input Port: .......................................................................................... PORTBUFI Buffer Output Port: ......................................................................................PORTBUFO Ground Port: ..................................................................................................PORTGND Input / Output Port:............................................................................................ PORTIO Ring Corner Port:..............................................................................................PORTRC VDD Port:........................................................................................................ PORTVDD Tanner Research, Inc. 2X2 Input AND-OR Description: AO22 2 X 2 Input AND-OR Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: AO22 File: TannerLb\scmos\scmos.tdb Cell: AO22 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A B Out C D Height 53 λ Width 57 λ A*B 0 1 X C*D 0 X 1 Area 3021 λ2 Capacitance Out 0 1 1 A B C D Equivalent Gate 2.5 Ci(fF) 6.953 6.953 6.953 6.953 Drive 1X Logic Equation Out = (A × B) + (C × D) Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........135 + 780 × C[OUT] Tpd1 → 0..........92 + 790 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A AO22 Page 1 of 4 2X2 Input AND-OR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. AO22 Rev. A AO22 Page 4 of 4 2X2 Input AND-NOR Description: AOI22 2 X 2 Input AND-NOR Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: AOI22 File: TannerLb\scmos\scmos.tdb Cell: AOI22 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A B Out C D Height 53 λ Width 41 λ A*B 0 1 X C*D 0 X 1 Area 2173 λ2 Capacitance Out 1 0 0 A B C D Equivalent Gate 2 Ci(fF) 6.953 6.953 6.953 6.953 Drive 1X Logic Equation Out = (A × B) + (C × D) Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........60 + 822 × C[OUT] Tpd1 → 0..........97 + 1084 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A AOI22 Page 1 of 4 2X2 Input AND-NOR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. AOI22 Rev. A AOI22 Page 4 of 4 Non-Inverting Buffer Description: BUF1 Non-Inverting Buffer Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: Buf1 File: TannerLb\scmos\scmos.tdb Cell: Buf1 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A Truth Table A 0 1 Out Height 53 λ Width 25 λ Capacitance Out 0 1 Area 1325 λ2 A Equivalent Gate 1 Ci(fF) 6.953 Drive 1X Logic Equation Out = A Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........31 + 537 × C[OUT] Tpd1 → 0..........31 + 567 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A BUF1 Page 1 of 4 Non-Inverting Buffer Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. BUF1 Rev. A BUF1 Page 4 of 4 4X-Drive Buffer Description: BUF4 4X-Non-Inverting Buffer Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUF4 File: TannerLb\scmos\scmos.tdb Cell: BUF4 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A 4 Truth Table A 0 1 Out Height 53 λ Width 50 λ Capacitance Out 0 1 Area 2650 λ2 A Equivalent Gate 2.5 Ci(fF) 6.953 Drive 4X Logic Equation Out = A Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........49 + 156 × C[OUT] Tpd1 → 0..........49 + 167 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A BUF4 Page 1 of 4 4X-Drive Buffer Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. BUF4 Rev. A BUF4 Page 4 of 4 Buffer Clock Left Description: BUFCLKL Buffer Clock Left Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUFCLKL File: TannerLb\scmos\scmos.tdb Cell: BUFCLKL TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol CLK Truth Table CLK 0 1 Out Capacitance OUT 0 1 N/A BufClk_Left Height 53 λ Width 25.5 λ Area 1351.5 λ2 Equivalent Gate N/A Drive N/A Logic Equation Out = CLK Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUFCLKL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Buffer Clock Left Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library BUFCLKL Rev. A BUFCLKL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Buffer Clock Right Description: BUFCLKR Buffer Clock Right Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUFCLKR File: TannerLb\scmos\scmos.tdb Cell: BUFCLKR TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol CLK Truth Table CLK 0 1 Out Capacitance OUT 0 1 N/A BufClk_Right Height 53 λ Width 25.5 λ Area 1351.5 λ2 Equivalent Gate N/A Drive N/A Logic Equation Out = CLK Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUFCLKR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Buffer Clock Right Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library BUFCLKR Rev. A BUFCLKR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 4X-Drive Inverter Description: BUFI4 4X-Non-Inverting Buffer Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUFI4 File: TannerLb\scmos\scmos.tdb Cell: BUFI4 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol 4 A Truth Table A 0 1 Out Height 53 λ Width 41 λ Capacitance Out 1 0 Area 2173 λ2 A Equivalent Gate 2 Ci(fF) 27.811 Drive 4X Logic Equation Out = A Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........14 + 138 × C[OUT] Tpd1 → 0..........16 + 141 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A BUFI4 Page 1 of 4 4X-Drive Inverter Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. BUFI4 Rev. A BUFI4 Page 4 of 4 Buffer Reset Left Description: BUFRSTL Buffer Reset Left Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUFRSTL File: TannerLb\scmos\scmos.tdb Cell: BUFRSTL TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol RST Truth Table RST 0 1 Out Capacitance OUT 0 1 N/A BufRst_Left Height 53 λ Width 25 λ Area 1325 λ2 Equivalent Gate N/A Drive N/A Logic Equation Out = RST Delay Characteristics: N/A MOSIS AMI 0.5µ –mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUFRSTL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Buffer Reset Left Layout MOSIS AMI 0.5µ –mAMIs05DL Scalable Digital Standard Cell Library BUFRSTL Rev. A BUFRSTL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Buffer Reset Right Description: BUFRSTR Buffer Reset Right Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUFRSTR File: TannerLb\scmos\scmos.tdb Cell: BUFRSTR TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol RST Truth Table RST 0 1 Out Capacitance OUT 0 1 N/A BufRst_Right Height 53 λ Width 25 λ Area 1325 λ2 Equivalent Gate N/A Drive N/A Logic Equation Out = RST Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUFRSTR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Buffer Reset Right Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library BUFRSTR Rev. A BUFRSTR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Tri-State Buffer Description: BUFZ Tri-State Buffer Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUFZ File: TannerLb\scmos\scmos.tdb Cell: BUFZ TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Truth Table OEB A Primitive Set: OEB 1 0 0 Out Height 53 λ Width 59 λ A X 0 1 Area 3127 λ2 Capacitance Out Z 0 1 OEB A Equivalent Gate 2.5 Ci(fF) 13.905 6.953 Drive 1X Logic Equation Out = A Delay Characteristics: Tpd = t 0 + dt × CL dc Tr..........94 + 805 × C[OUT] Tf..........89 + 787 × C[OUT] Tzh........36 + 87 × C[OUT] Tzl.........22 + 128 × C[OUT] Thz........41 + 7 × C[OUT] Tlz.........12 + 125 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A BUFZ Page 1 of 4 Tri-State Buffer Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. BUFZ Rev. A BUFZ Page 4 of 4 Bus Clock Left Description: BUSCLKL Bus Clock Left Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUSCLKL File: TannerLb\scmos\scmos.tdb Cell: BUSCLKL TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance N/A N/A N/A Height 53 λ Width 24 λ Area 1272 λ2 Equivalent Gate N/A Drive N/A Logic Equation N/A Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUSCLKL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Bus Clock Left Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library BUSCLKL Rev. A BUSCLKL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Bus Clock Right Description: BUSCLKR Bus Clock Right Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUSCLKR File: TannerLb\scmos\scmos.tdb Cell: BUSCLKR TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance N/A N/A N/A Height 53 λ Width 24 λ Area 1272 λ2 Equivalent Gate N/A Drive N/A Logic Equation N/A Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUSCLKR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Bus Clock Right Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library BUSCLKR Rev. A BUSCLKR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Bus Reset Left Description: BUSRSTL Bus Reset Left Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUSRSTL File: TannerLb\scmos\scmos.tdb Cell: BUSRSTL TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance N/A N/A N/A Height 53 λ Width 24 λ Area 1272 λ2 Equivalent Gate N/A Drive N/A Logic Equation N/A Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUSRSTL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Bus Reset Left Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library BUSRSTL Rev. A BUSRSTL Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Bus Reset Right Description: BUSRSTR Bus Reset Right Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: BUSRSTR File: TannerLb\scmos\scmos.tdb Cell: BUSRSTR TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance N/A N/A N/A Height 53 λ Width 24 λ Area 1272 λ2 Equivalent Gate N/A Drive N/A Logic Equation N/A Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A BUSRSTR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Bus Reset Right Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library BUSRSTR Rev. A BUSRSTR Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 D Flip-Flop DFF_s Description: D Flip-Flop Library: Tanner mAMIs05DL Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: DFF_s File: TannerLb\scmos\scmos.tdb Cell: DFF_s TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Data D Truth Table Q Q Clk Q Clk 1 0 ↑ ↑ QB Height 53 λ Width 154.5 λ Data X X 0 1 Q(t+1) Q(t) Q(t) 0 1 Capacitance QB(t+1) QB(t) QB(t) 1 0 Area 8188.5 λ2 Clk Data Equivalent Gate 7 Ci(fF) 6.953 6.953 Drive 1X Logic Equation I(t + 1) = Data × Clk + (I(t ) × Clk ) Q(t + 1) = (I(t ) × Clk) + Q(t ) × Clk QB(t + 1) = Q(t + 1) ( ) ( Delay Characteristics: Tr Q..........179 + 545 × C[Q] Tf Q..........152 + 579 × C[Q] Tr QB........122 + 555 × C[QB] Tf QB........150 + 595 × C[QB] ) dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A DFF_s Page 1 of 4 D Flip-Flop Layout MOSIS AMI 0.5µ –mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. DFF_s Rev. A DFF_s Page 4 of 4 D Flip-Flop AC Description: DFFC_s D Flip-Flop with Asynchronous Clear Library: Tanner mAMIs05DL Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: DFFC_s File: TannerLb\scmos\scmos.tdb Cell: DFFC_s TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Truth Table ClB Logic Symbol Clk X 1 0 ↑ ↑ Cl D Clk Q Q Q Data QB Height 53 λ ClB 0 1 1 1 1 Width 197 λ Data X X X 0 1 Capacitance Q(t+1) 0 Q(t) Q(t) 0 1 Area 10441 λ2 QB(t+1) 1 QB(t) QB(t) 1 0 Clk ClB Data Equivalent Gate 8.5 Ci(fF) 6.953 13.905 6.953 Drive 1X Logic Equation I(t + 1) = Data × Clk + (I(t ) × Clk) × ClB Q(t + 1) = (I (t ) × Clk) + Q(t ) × Clk × ClB QB(t + 1) = Q(t + 1) ( ) ( Delay Characteristics: Tr Q.......... 283 + 990 × C[Q] Tf Q.......... 104 + 828 × C[Q] Trst Q........87 + 920 × C[Q] Tr QB........115 + 630 × C[QB] Tf QB........168 + 611 × C[QB] Trst QB......135 + 549 × C[QB] ) dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A DFFC_s Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 D Flip-Flop AC Layout MOSIS AMI 0.5µ –mAMIs05DL Scalable Digital Standard Cell Library DFFC_s Rev. A DFFC_s Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 D Flip-Flop Preset Description: DFFP_s D Flip-Flop with Preset Library: Tanner mAMIs05DL Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: DFFP_s File: TannerLb\scmos\scmos.tdb Cell: DFFP_s TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Data D Truth Table Q Q Clk Clk X 1 0 ↑ ↑ Q QB Pr PrB Height 53 λ PrB 0 1 1 1 1 Width 175.5 λ Data X X X 0 1 Capacitance Q(t+1) 1 Q(t) Q(t) 0 1 Area 9301.5 λ2 QB(t+1) 0 QB(t) QB(t) 1 0 Clk PrB Data Equivalent Gate 8 Ci(fF) 6.953 13.905 6.953 Drive 1X Logic Equation I(t + 1) = Data × Clk + (I(t ) × Clk ) × PrB Q(t + 1) = (I(t ) × Clk) + Q(t ) × Clk × PrB QB(t + 1) = Q(t + 1) ( ) ( Delay Characteristics: Tr Q.......... 219 + 571 × C[Q] Tf Q.......... 208 + 624 × C[Q] Tset Q........103 + 732 × C[Q] Tr QB........166 + 675 × C[QB] Tf QB........179 + 631 × C[QB] Tset QB.....41 + 610 × C[QB] ) dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A DFFP_s Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 D Flip-Flop Preset Layout MOSIS AMI 0.5µ –mAMIs05DL Scalable Digital Standard Cell Library DFFP_s Rev. A DFFP_s Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 D Flip-Flop P/AC Description: DFFPC_s D Flip-Flop with Preset and Asynchronous Clear Library: Tanner mAMIs05DL Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: DFFPC_s File: TannerLb\scmos\scmos.tdb Cell: DFFPC_s TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Truth Table Clk X X X X 1 0 ↑ ↑ ClB Cl D Q Clk Q Q Data QB Pr PrB Height 53 λ Width 217 λ PrB 0 1 0 ↑ 1 1 1 1 ClB 1 0 0 ↑ 1 1 1 1 Data X X X X X X 0 1 Area 11501 λ2 Capacitance Q(t+1) 1 0 1 ? Q(t) Q(t) 0 1 QB(t+1) 0 1 1 ? QB(t) QB(t) 1 0 Clk PrB ClB Data Ci(fF) 6.953 13.905 13.905 6.953 ? Indeterminate value Equivalent Gate 9.5 Drive 1X Logic Equation I(t + 1) = Data × Clk + (I(t ) × Clk ) × ClB × PrB Q(t + 1) = (I(t ) × Clk ) + Q(t ) × Clk × ClB × PrB QB(t + 1) = Q(t + 1) ( ) ( Delay Characteristics: Tr Q.......... 323 + 843 × C[Q] Tf Q.......... 233 + 713 × C[Q] Tset Q........159 + 847 × C[Q] Trst Q........83 + 843 × C[Q] Tr QB........160 + 655 × C[QB] Tf QB....... 208 + 622 × C[QB] Tset QB.....39 + 594 × C[QB] Trst QB.....168 + 653 × C[QB] ) dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A DFFPC_s Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 D Flip-Flop P/AC Layout MOSIS AMI 0.5µ –mAMIs05DL Scalable Digital Standard Cell Library DFFPC_s Rev. A DFFPC_s Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Inverter INV Description: Inverter Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: INV File: TannerLb\scmos\scmos.tdb Cell: INV TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A Truth Table A 0 1 Out Height 53 λ Width 18 λ Capacitance A Out 1 0 Area 954 λ2 Equivalent Gate 0.5 Ci(fF) 6.953 Drive 1X Logic Equation Out = A Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........12 + 529 × C[OUT] Tpd1 → 0..........12 + 549 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A INV Page 1 of 4 Inverter Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. INV Rev. A INV Page 4 of 4 Dual Inverter INV2 Description: Dual Inverter Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: INV2 File: TannerLb\scmos\scmos.tdb Cell: INV2 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A I0 O0 Out1 B I1 O1 A 0 0 1 1 Out2 Height 53 λ Width 33 λ B 0 1 0 1 Out1 1 1 0 0 Area 1749 λ2 Capacitance Out2 1 0 1 0 A B Equivalent Gate 1 Ci(fF) 6.953 6.953 Drive 1X Logic Equation Out1 = A Out2 = B Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1 ..........11 + 529 × C[OUT1] Tpd1 → 0 ..........12 + 539 × C[OUT1] Tpd0 → 1 ..........14 + 538 × C[OUT2] Tpd1 → 0 ..........14 + 500 × C[OUT2] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A INV2 Page 1 of 4 Dual Inverter Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. INV2 Rev. A INV2 Page 4 of 4 Tri-State Inverter Description: Tri-State Inverter Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: INVZ File: TannerLb\scmos\scmos.tdb Cell: INVZ TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Truth Table OEB Logic Symbol A INVZ OEB 1 0 0 Out Height 53 λ Width 43 λ A X 0 1 Area 2279 λ2 Capacitance Out Z 1 0 OEB A Equivalent Gate 2.5 Ci(fF) 13.905 13.905 Drive 1X Logic Equation Out = A Delay Characteristics: Tpd = t 0 + dt × CL dc Tr..........25 + 534 × C[OUT] Tf..........27 + 521 × C[OUT] Tzh........1 Tzl.........16 + 36 × C[OUT] Thz........1 Tlz.........17 MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A INVZ Page 1 of 4 Tri-State Inverter Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. INVZ Rev. A INVZ Page 4 of 4 Latch LAT Description: Latch Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: LAT File: TannerLb\scmos\scmos.tdb Cell: LAT TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Data D Q Q GB G Q GB 0 0 1 QB Height 53 λ Width 79 λ Data 0 1 X Q(t+1) 0 1 Q(t) Area 4187 λ2 Capacitance QB(t+1) 1 0 QB(t) GB Data Equivalent Gate 3.5 Ci(fF) 6.953 6.953 Drive 1X Logic Equation Q(t + 1) = Data × GB + (Q(t) × GB) QB(t + 1) = Q(t + 1) ( ) Delay Characteristics: Tr Tf Tr Tf Tr Tf Tr Tf DQ..........86 + 652 × C[Q] DQ..........85 + 697 × C[Q] GQ..........118 + 699 × C[Q] GQ..........105 + 650 × C[Q] DQB........110 + 1531 × C[QB] DQB........114 + 1512 × C[QB] GQB........143 + 1532 × C[QB] GQB........132 + 1512 × C[QB] dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A LAT Page 1 of 4 Latch Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. LAT Rev. A LAT Page 4 of 4 Latch with Clear Description: LATC Latch with Clear Library: Tanner mAMIs05DL Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: LATC File: TannerLb\scmos\scmos.tdb Cell: LATC TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Truth Table Capacitance ClB GB X 0 0 1 Cl Data D Q Q GB G Q QB Height 53 λ ClB 0 1 1 1 Width 96 λ Data X 0 1 X Q(t+1) 0 0 1 Q(t) Area 5088 λ2 QB(t+1) 1 1 0 QB(t) GB ClB Data Equivalent Gate 4.5 Ci(fF) 6.953 6.953 6.953 Drive 1X Logic Equation Q(t + 1) = Data × GB + (Q(t ) × GB ) × ClB QB(t + 1) = Q(t + 1) ( ) Delay Characteristics: Tr DQ..........150 + 2053 × C[Q] Tf DQ..........149 + 1493 × C[Q] Tr GQ..........144 + 1489 × C[Q] Tf GQ..........162 + 2053 × C[Q] Trst Q...........40 + 1419 × C[Q] Tr DQB .......120 + 628 × C[QB] Tf DQB........121 + 1027 × C[QB] Tr GQB........115 + 626 × C[QB] Tf GQB........132 + 1029 × C[QB] Trst QBKK15 + 531 × C[QB] dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A LATC Page 1 of 4 Latch with Clear Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. LATC Rev. A LATC Page 4 of 4 Latch with Preset Description: LATP Latch with Preset Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: LATP File: TannerLb\scmos\scmos.tdb Cell: LATP TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Data D Q GB G Q GB X 0 0 1 Q QB Pr PrB 0 1 1 1 Data X 0 1 X Capacitance Q(t+1) 1 0 1 Q(t) QB(t+1) 0 1 0 QB(t) GB PrB Data Ci(fF) 6.953 6.953 6.953 PrB Height 53 λ Width 87 λ Logic Equation ( )( Area 4611 λ2 Q(t + 1) = Data × GB + (Q(t ) × GB ) + PrB QB(t + 1) = Q(t + 1) Delay Characteristics: Tr DQ..........97 + 624 × C[Q] Tf DQ..........102 + 1029 × C[Q] Tr GQ..........135 + 1038 × C[Q] Tf GQ..........116 + 623 × C[Q] Tset Q...........16 + 523 × C[Q] Tr DQB.......132 + 2053 × C[QB] Tf DQB.......126 + 1489 × C[QB] Tr GQB.......166 + 2053 × C[QB] Tf GQB.......145 + 1487 × C[QB] Tset QB........42 + 1417 × C[QB] Equivalent Gate 4 Drive 1X ) dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A LATP Page 1 of 4 Latch with Preset Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. LATP Rev. A LATP Page 4 of 4 Latch with Pre/Clr Description: LATPC Latch with Preset and Clear Library: Tanner mAMIs05DL Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: LATPC File: TannerLb\scmos\scmos.tdb Cell: LATPC TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Truth Table Capacitance ClB Cl Data D GB Q G Q Q QB Pr GB X X 1 0 0 1 PrB 0 1 ↑ 1 1 1 ClB X 0 ↑ 1 1 1 Data 1 X X 0 1 X Q(t+1) 1 0 ? 0 1 Q(t) QB(t+1) 0 1 ? 1 0 QB(t) PrB GB PrB ClB Data Ci(fF) 6.953 6.953 6.953 6.953 ? Indeterminate value Height 53 λ Width 116 λ Area 6148 λ2 Equivalent Gate 5 Drive 1X Logic Equation Q(t + 1) = Data × GB + (Q(t ) × GB) × ClB × PrB QB(t + 1) = Q(t + 1) (( ) ) Delay Characteristics: Tr DQ.......... 109 + 1087 × C[Q] Tf DQ.......... 108 + 1050 × C[Q] Tr GQ.......... 139 + 1050 × C[Q] Tf GQ.......... 125 + 1084 × C[Q] Tset Q............23 + 565 × C[Q] Trst Q............763 + 1018 × C[Q] dt Tpd = t 0 + × C L dc Tr DQB..........140 + 2086 × C[QB] Tf DQB..........144 + 2159 × C[QB] Tr GQB..........171 + 2086 × C[QB] Tf GQB..........159 + 2157 × C[QB] Tset QB............54 + 1442 × C[QB] Trst QB............97 + 2061 × C[QB] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A LATPC Page 1 of 4 Latch with Pre/Clr Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. LATPC Rev. A LATPC Page 4 of 4 2-Input Multiplexer Description: MUX2 2-Input Multiplexer Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: MUX2 File: TannerLb\scmos\scmos.tdb Cell: MUX2 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A Sel 0 1 D0 Y B Truth Table Out D1 Capacitance Out B A A B Sel Sel S0 Ci(fF) 6.953 6.953 13.905 Height 53 λ Width 61 λ Logic Equation Out = (A × Sel )+ Equivalent Gate 3 Drive 1X (B × Sel ) Delay Characteristics: Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Area 3233 λ2 A..........84 + 700 × C[OUT] A..........72 + 821 × C[OUT] B..........91 + 710 × C[OUT] B..........76 + 857 × C[OUT] Sel........92 + 702 × C[OUT] Sel........95 + 757 × C[OUT] dt Tpd = t 0 + × C L dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A MUX2 Page 1 of 4 2-Input Multiplexer Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. MUX2 Rev. A MUX2 Page 4 of 4 2-Input NAND Description: NAND2 2-Input NAND Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NAND2 File: TannerLb\scmos\scmos.tdb Cell: NAND2 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X 1 A Out B Height 53 λ Width 26 λ B X 0 1 Area 1378 λ2 Capacitance Out 1 1 0 A B Equivalent Gate 1 Ci(fF) 6.953 6.953 Drive 1X Logic Equation Out = A X B Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........18 + 545 × C[OUT] Tpd1 → 0..........19 + 1159 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A NAND2 Page 1 of 4 2-Input NAND Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. NAND2 Rev. A NAND2 Page 4 of 4 2-Input NAND / AND Description: NAND2C 2-Input NAND Gate with Complementary Output Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NAND2C File: TannerLb\scmos\scmos.tdb Cell: NAND2C TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X 1 A Out1 B Out2 Height 53 λ Width 38 λ B X 0 1 Out1 1 1 0 Area 2014 λ2 Capacitance Out2 0 0 1 A B Equivalent Gate 1.5 Ci(fF) 6.953 6.953 Drive 1X Logic Equation Out1 = A × B Out2 = A × B Delay Characteristics: Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Tpd = t 0 + dt × CL dc NAND..........23 + 543 × C[OUT1] NAND..........34 + 989 × C[OUT1] AND.............56 + 989 × C[OUT1] + 1042 × C[OUT2] AND.............43 + 543 × C[OUT1] + 888 × C[OUT2] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A NAND2C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 2-Input NAND / AND Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library NAND2C Rev. A NAND2C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 3-Input NAND Description: NAND3 3-Input NAND Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NAND3 File: TannerLb\scmos\scmos.tdb Cell: NAND3 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A B C Truth Table A 0 X X 1 Out Height 53 λ Width 34 λ B X 0 X 1 C X X 0 1 Area 1802 λ2 Capacitance Out 1 1 1 0 A B C Equivalent Gate 1.5 Ci(fF) 6.953 6.953 6.953 Drive 1X Logic Equation Out = A × B × C Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........33 + 554 × C[OUT] Tpd1 → 0..........83 + 1415 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A NAND3 Page 1 of 4 3-Input NAND Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. NAND3 Rev. A NAND3 Page 4 of 4 3-Input NAND / AND Description: NAND3C 3-Input NAND Gate with Complementary Output Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NAND3C File: TannerLb\scmos\scmos.tdb Cell: NAND3C TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A B C Truth Table A 0 X X 1 Out1 Out2 Height 53 λ Width 48 λ B X 0 X 1 C X X 0 1 Capacitance Out1 1 1 1 0 Area 2544 λ2 Out2 0 0 0 1 A B C Equivalent Gate 2 Ci(fF) 6.953 6.953 6.953 Drive 1X Logic Equation Out1 = A × B × C Out2 = A × B × C Delay Characteristics: Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Tpd = t 0 + dt × CL dc NAND..........37 + 554 × C[OUT1] NAND..........93 + 1413 × C[OUT1] AND...........123 + 1413 × C[OUT1] + 1227 × C[OUT2] AND........... 61 + 554 × C[OUT1] + 919 × C[OUT2] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A NAND3C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 3-Input NAND / AND Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library NAND3C Rev. A NAND3C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 4-Input NAND Description: NAND4 4-Input NAND Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NAND4 File: TannerLb\scmos\scmos.tdb Cell: NAND4 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X X X 1 A B Out C D Height 53 λ Width 41 λ B X 0 X X 1 C X X 0 X 1 Area 2173 λ2 D X X X 0 1 Capacitance Out 1 1 1 1 0 A B C D Equivalent Gate 2 Ci(fF) 6.953 6.953 6.953 6.953 Drive 1X Logic Equation Out = A × B × C × D Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........40 + 578 × C[OUT] Tpd1 → 0..........138 + 1850 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A NAND4 Page 1 of 4 4-Input NAND Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. NAND4 Rev. A NAND4 Page 4 of 4 4-Input NAND / AND Description: NAND4C 4-Input NAND Gate with Complementary Output Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NAND4C File: TannerLb\scmos\scmos.tdb Cell: NAND4C TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X X X 1 A B Out1 C D Out2 Height 53 λ Width 54 λ B X 0 X X 1 C X X 0 X 1 D X X X 0 1 Area 2862 λ2 Capacitance Out1 1 1 1 1 0 Out2 0 0 0 0 1 A B C D Equivalent Gate 2.5 Ci(fF) 6.953 6.953 6.953 6.953 Drive 1X Logic Equation Out1 = A × B × C × D Out2 = A × B × C × D Delay Characteristics: Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Tpd = t 0 + dt × CL dc NAND..........43 + 574 × C[OUT1] NAND..........149 + 1848 × C[OUT1] AND.............186 + 1848 × C[OUT1] + 1377 × C[OUT2] AND..............68 + 574 × C[OUT1] + 940 × C[OUT2] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A NAND4C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 4-Input NAND / AND Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library NAND4C Rev. A NAND4C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 2-Input NOR Description: NOR2 2-Input NOR Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NOR2 File: TannerLb\scmos\scmos.tdb Cell: NOR2 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X 1 A Out B Height 53 λ Width 25 λ B 0 1 X Area 1325 λ2 Capacitance Out 1 0 0 A B Equivalent Gate 1 Ci(fF) 6.953 6.953 Drive 1X Logic Equation Out = A + B Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........31 + 1044 × C[OUT] Tpd1 → 0..........20 + 587 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A NOR2 Page 1 of 4 2-Input NOR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. NOR2 Rev. A NOR2 Page 4 of 4 2-Input NOR / OR Description: NOR2C 2-Input NOR Gate with Complementary Output Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NOR2C File: TannerLb\scmos\scmos.tdb Cell: NOR2C TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X 1 A Out1 B Out2 Height 53 λ Width 37 λ B 0 1 X Capacitance Out1 1 0 0 Area 1961 λ2 Out2 0 1 1 A B Equivalent Gate 1.5 Ci(fF) 6.953 6.953 Drive 1X Logic Equation Out1 = A + B Out2 = A + B Delay Characteristics: Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Tpd = t 0 + dt × CL dc NOR..........37 + 1042 × C[OUT1] NOR..........23 + 585 × C[OUT1] OR.............42 + 585 × C[OUT1] + 852 × C[OUT2] OR.............59 + 1042 × C[OUT1] + 1083 × C[OUT2] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A NOR2C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 2-Input NOR / OR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library NOR2C Rev. A NOR2C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 3-Input NOR Description: NOR3 3-Input NOR Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NOR3 File: TannerLb\scmos\scmos.tdb Cell: NOR3 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A B C Truth Table A 0 X X 1 Out Height 53 λ Width 35 λ B 0 X 1 X C 0 1 X X Area 1855 λ2 Capacitance Out 1 0 0 0 A B C Equivalent Gate 1.5 Ci(fF) 6.953 6.953 6.953 Drive 1X Logic Equation Out = A + B + C Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........82 + 1556 × C[OUT] Tpd1 → 0..........31 + 622 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A NOR3 Page 1 of 4 3-Input NOR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. NOR3 Rev. A NOR3 Page 4 of 4 3-Input NOR / OR Description: NOR3C 3-Input NOR Gate with Complementary Output Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NOR3C File: TannerLb\scmos\scmos.tdb Cell: NOR3C TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A B C Truth Table A 0 X X 1 Out1 Out2 Height 53 λ Width 45 λ B 0 X 1 X C 0 1 X X Capacitance Out1 1 0 0 0 Area 2385 λ2 Out2 0 1 1 1 A B C Equivalent Gate 2 Ci(fF) 6.953 6.953 6.953 Drive 1X Logic Equation Out1 = A + B + C Out2 = A + B + C Delay Characteristics: Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Tpd = t 0 + dt × CL dc NOR..........89 + 1556 × C[OUT1] NOR..........34 + 625 × C[OUT1] OR.............57 + 625 × C[OUT1] + 887 × C[OUT2] OR...........118 + 1556 × C[OUT1] + 1259 × C[OUT2] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A NOR3C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 3-Input NOR / OR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library NOR3C Rev. A NOR3C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 4-Input NOR Description: NOR4 4-Input NOR Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NOR4 File: TannerLb\scmos\scmos.tdb Cell: NOR4 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X X X 1 A B Out C D Height 53 λ Width 41 λ B 0 X X 1 X C 0 X 1 X X Area 2173 λ2 D 0 1 X X X Capacitance Out 1 0 0 0 0 A B C D Equivalent Gate 2 Ci(fF) 6.953 6.953 6.953 6.953 Drive 1X Logic Equation Out = A + B + C + D Delay Characteristics: Tpd = t 0 + dt × CL dc Tpd0 → 1..........131 + 2081 × C[OUT] Tpd1 → 0.......... 33 + 660 × C[OUT] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A NOR4 Page 1 of 4 4-Input NOR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. NOR4 Rev. A NOR4 Page 4 of 4 4-Input NOR / OR Description: NOR4C 4-Input NOR Gate with Complementary Output Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: NOR4C File: TannerLb\scmos\scmos.tdb Cell: NOR4C TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 X X X 1 A B Out1 C D Out2 Height 53 λ Width 49 λ B 0 X X 1 X C 0 X 1 X X D 0 1 X X X Area 2597 λ2 Capacitance Out1 1 0 0 0 0 Out2 0 1 1 1 1 A B C D Equivalent Gate 2.5 Ci(fF) 6.953 6.953 6.953 6.953 Drive 1X Logic Equation Out1 = A + B + C + D Out2 = A + B + C + D Delay Characteristics: Tpd0 → 1 Tpd1 → 0 Tpd0 → 1 Tpd1 → 0 Tpd = t 0 + dt × CL dc NOR..........145 + 2076 × C[OUT1] NOR...........37 + 652 × C[OUT1] OR...............61 + 652 × C[OUT1] + 912 × C[OUT2] OR............178 + 2076 × C[OUT1] + 1408 × C[OUT2] MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A NOR4C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 4-Input NOR / OR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library NOR4C Rev. A NOR4C Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Schmitt Trigger Inverter Description: Schmitt Trigger Inverter Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: SINV File: TannerLb\scmos\scmos.tdb Cell: SINV TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol A SINV Truth Table A 0 1 Y Height 53 λ Width 53 λ Capacitance A Y 1 0 Area 2809 λ2 Equivalent Gate 1.5 Ci(fF) 13.905 Drive 1X Logic Equation Out = A Delay Characteristics: Tpd0 → 1..........37 + 971 × C[OUT] Tpd1 → 0..........34 + 983 × C[OUT] Tpd = t 0 + dt × CL dc VT + ............1.97V (VDD = 3.3V) VT - ............1.28V (VDD = 3.3V) MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A SINV Page 1 of 4 Schmitt Trigger Inverter Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. SINV Rev. A SINV Page 4 of 4 2-Input Exclusive-NOR Description: XNOR2 2-Input Exclusive-NOR Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: XNOR2 File: TannerLb\scmos\scmos.tdb Cell: XNOR2 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 0 1 1 A Out B Height 53 λ Width 54 λ B 0 1 0 1 Area 2862 λ2 Capacitance Out 1 0 0 1 A B Equivalent Gate 2.75 Ci(fF) 13.905 13.905 Drive 1X Logic Equation Out = (A × B) + ( A × B) Delay Characteristics: Tpd0 → 1..........65 + 592 × C[OUT] Tpd1 0..........46 + 955 × C[OUT] Tpd = t 0 + dt × CL dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A XNOR2 Page 1 of 4 2-Input Exclusive-NOR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. XNOR2 Rev. A XNOR2 Page 4 of 4 2-Input Exclusive-OR Description: XOR2 2-Input Exclusive-OR Gate Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: XOR2 File: TannerLb\scmos\scmos.tdb Cell: XOR2 TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table A 0 0 1 1 A Out B Height 53 λ Width 54 λ B 0 1 0 1 Area 2862 λ2 Capacitance Out 0 1 1 0 A B Equivalent Gate 2.75 Ci(fF) 13.905 13.905 Drive 1X Logic Equation Out = (A × B) + ( A × B) Delay Characteristics: Tpd0 → 1..........48 + 991 × C[OUT] Tpd1 → 0..........64 + 634 × C[OUT] Tpd = t 0 + dt × CL dc MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. Rev. A XOR2 Page 1 of 4 2-Input Exclusive-OR Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Copyright © 1999 by Tanner Research, Inc. All rights reserved. XOR2 Rev. A XOR2 Page 4 of 4 Input Port Description: PORTBUFI Buffered Input Port with Complementary Signals Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: PortBufI File: TannerLb\scmos\scmos.tdb Cell: PortBufI TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol DIB DI Pad Truth Table DIB DI PAD 0 1 DI 0 1 Capacitance DIB 1 0 N/A PortBufI Height 70 λ Width 94 λ Area 6580 λ2 Equivalent Gate N/A Drive N/A Logic Equation DI = In DIB = In Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A PORTBUFI Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Input Port Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library PORTBUFI Rev. A PORTBUFI Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Output Port Description: PORTBUFO Buffered Output Port used for Core routing Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: PortBufO File: TannerLb\scmos\scmos.tdb Cell: PortBufO TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol DO Truth Table DO 0 1 Pad Capacitance PAD 0 1 N/A PortBufO Height 70 λ Width 94 λ Area 6580 λ2 Equivalent Gate N/A Drive N/A Logic Equation DO = Out Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A PORTBUFO Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Output Port Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library PORTBUFO Rev. A PORTBUFO Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Ground Port Description: PORTGND Ground Port used for core routing Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: PortGnd File: TannerLb\scmos\scmos.tdb Cell: PortGnd TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Truth Table N/A PAD Capacitance N/A PortGnd Height 70 λ Width 94 λ Area 6580 λ2 Equivalent Gate N/A Drive N/A Logic Equation Port = 0 Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A PORTGND Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Ground Port Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library PORTGND Rev. A PORTGND Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Input/Output Port Description: Input/Output Port Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol PAD PORTIO Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: PortIO File: TannerLb\scmos\scmos.tdb Cell: PortIO TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Truth Table Capacitance N/A N/A SIGNAL PortIO Height 70 λ Width 20 λ Area 1400 λ2 Equivalent Gate N/A Drive N/A Logic Equation Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A PORTIO Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Input/Output Port Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library PORTIO Rev. A PORTIO Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Ring Corner Port Description: PORTRC Ring Corner Port Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: PortRC File: TannerLb\scmos\scmos.tdb Cell: PortRC TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Logic Symbol Truth Table Capacitance N/A N/A N/A Height 70 λ Width 70 λ Area 4900 λ2 Equivalent Gate N/A Drive N/A Logic Equation N/A Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A PORTRC Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Ring Corner Port Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library PORTRC Rev. A PORTRC Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 Power Port Description: PORTVDD Power Port used for core routing Library: Tanner mAMIs05DL Schematic: S-Edit Mask layout: L-Edit Mapping Macros: GateSim: L-Edit/SPR: Logic Symbol Primitive Set: Tanner SCMOS.Cells Tanner.TIB.Samples File: TannerLb\scmos\scmos.sdb Module: PortVdd File: TannerLb\scmos\scmos.tdb Cell: PortVdd TannerLb\nettran\scmos\scms2sim.mac TannerLb\nettran\scmos\scms2tpr.mac Truth Table N/A PAD Capacitance N/A PortVdd Height 70 λ Width 94 λ Area 6580 λ2 Equivalent Gate N/A Drive N/A Logic Equation Port = 1 Delay Characteristics: N/A MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library Rev. A PORTVDD Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 1 of 4 Power Port Layout MOSIS AMI 0.5µ – mAMIs05DL Scalable Digital Standard Cell Library PORTVDD Rev. A PORTVDD Copyright © 1999 by Tanner Research, Inc. All rights reserved. Page 4 of 4 ...
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This note was uploaded on 12/04/2011 for the course CPE 427 taught by Professor Staff during the Fall '10 term at University of Alabama - Huntsville.

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