This preview has intentionally blurred sections. Sign up to view the full version.
View Full DocumentThis preview has intentionally blurred sections. Sign up to view the full version.
View Full Document
Unformatted text preview: SOLUTIONS TO PROBLEMS FROM CHAPTER 8 8.1. Figure P8.1. shows the I D V GS characteristic for an NMOS with V DS =50 mV. It is known for this device that W= 10 μ m, L =0.5 μ m, and t ox =5 nm. a) Find the threshold voltage Since V DS =50 mV and L =0.5 μ m, the average field in the channel is 0.1 V/ μ m=1kV/cm and the device is not in the velocity saturation region. Thus the expression (Equation (8.4)) ( 29 ( 29 ' 1 2 ox DS DS D GS T GS T WC V V I V V L V V μ θ = + can be used. The threshold is extrapolated from the linear region, and using Equation (8.8), 0.05 0.5 2 2 DS T T V V V V + = = + Therefore V T =0.475V. b) Find μ , the electron channel mobility at threshold. The slope of the linear region is about 160 μ A/(0.5V)=0.32mA/V. From Equation (8.7), we have ' D ox DS GS dI WC V dV L μ = Anderson & Anderson 1 May 13, 2009 Solutions Chapter 8 C ox ' = ε ox t ox = 3.9 ( 29 8.85 × 10 14 F / cm ( 29 5 × 10 7 cm = 6.9 × 10 7 F / cm 2 Solving for μ we have ( 29 3 2 ' 7 2 0.5 0.32 10 / 460 10 6.9 10 / 0.05 D GS ox DS dI L dV A V cm WC V F cm V V s μ μ = = = μ 8.2. A particular MOSFET process produces C B ' =107 F/cm 2 and I = 4 × 10 20 A , and a threshold voltage of V T =0.5V. For gate oxide thicknesses of 6.5 nm and 4 nm, find n and S . Which device is better, and why? For t ox =6.5 nm, C ox ' = ε ox t ox = 3.9 8.85 × 10 14 F / cm ( 29 6.5 × 10 7 cm = 5.3 × 10 7 F / cm n = 1 + C B ' C ox ' = 1 + 10 7 5.3 × 10 7 = 1.19 S = 2.3 kTn q = 71 mV / decade For the 4 nm oxide, ' 7 8.63 10 / ox C F cm = × =, and n = 1 + C B ' C ox ' = 1 + 10 7 8.63 × 10 7 = 1.12 S = 2.3 kTn q = 2.3 ( 29 0.026 ( 29 1.12 ( 29 = 67 mV / decade The 4 nm device is better. The swing S is smaller, resulting in a sharper turnon and thus permitting a reduced threshold voltage and a reduced power supply voltage and reduced power consumption. 8.3. a) Find W p / W n needed to match I Dsat for CMOS transistors if μ lfn = 500 cm 2 / V ⋅ s , μ lfp =200 cm 2 /V∙s, L= 0.5 μ m, and V GS V T =2.6 V. Assume that 6 4 10 / sat v cm s = × s. From Figure 8.6, we want W p W n = 1.3 . b) Find V DSsat for the NMOS and the PMOS. Anderson & Anderson 2 May 13, 2009 Solutions Chapter 8 ( 29 ( 29 ( 29 ( 29 1 2 ( ) 1 2 2 6 4 2 6 4 2 v 1 1 v 2 500 2.6 4 10 0.5 10 1 1 4 10 0.5 10 500 1.09 lfn GS T sat DSsat n nFET lfn sat nFET V V V L L cm cm V V s s cm cm cm cm s V s V μ μ = + μ μ = + μ μ = (or one could read it off Figure 7.31) Similarly, ( 29 ( 29 ( 29 ( 29 1 2 ( ) 1 2 2 6 4 2 6 4 2 1 1 2 200 2.6 4 10 0.5 10 1 1 4 10 0.5 10 200 1.49 lfp GS T sat DSsat p pFET lfp sat pFET V V v V L v L cm cm V V s s cm cm cm cm s V s V μ μ = + μ μ = + μ μ = c) Adjust the length of the NFET to equalize the V DSsat ’s . What should the new W p W n be to keep the...
View
Full
Document
This homework help was uploaded on 04/06/2008 for the course ECE 3323 taught by Professor Mccann during the Spring '06 term at The University of Oklahoma.
 Spring '06
 McCann
 Volt

Click to edit the document details