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Writeup Exp 4

# Writeup Exp 4 - Mynda Songer EE 361-03 Logic Gates and...

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Mynda Songer EE 361-03 Logic Gates and Flip-Flops Experiment 4 The NAND Gate A B F 0 0 1 0 1 1 1 0 1 1 1 0 Table 1: Truth Table for a NAND gate Figure 1: Plot of V in (above) and V out (below) for an inverter circuit using a NAND gate. The output does not change when the “A” input is allowed to “float” by disconnecting it from the 5 volt source.

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Figure 2: Plot of V in (below) and V out (above) for the inverter circuit with a triangle wave input. The point of intersection is the only point when the output becomes a “1,” because it’s the only point where the input is a “0.”
Cross-Coupled NAND Gates Not S Not R Q Not Q 1 0 0 1 0 1 1 0 Table 2: Truth Table for an R-S Flip-Flop made from cross-coupled NAND gates. J-K Flip-Flops J K Q Not Q 0 0 0 1 Storage 0 1 0 1 Reset 1 0 1 0 Set 1 1 0 1 Toggle Table 3: Truth Table for an J-K Flip-Flop with each mode identified. Figure 3: Plot of Clock input (below) and Q output (above) for the frequency divider circuit with a J-K Flip-Flop in toggle mode (J=K=1).

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Writeup Exp 4 - Mynda Songer EE 361-03 Logic Gates and...

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