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04_pipeline

# 04_pipeline - This Unit(Scalar In-Order Pipelining App App...

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CIS 501 (Martin): Pipelining 1 CIS 501 Computer Architecture Unit 4: Pipelining Slides developed by Milo Martin & Amir Roth at the University of Pennsylvania with sources that included University of Wisconsin slides by Mark Hill, Guri Sohi, Jim Smith, and David Wood. CIS 501 (Martin): Pipelining 2 This Unit: (Scalar In-Order) Pipelining • Principles of pipelining • Effects of overhead and hazards • Pipeline diagrams • Data hazards • Stalling and bypassing • Control hazards • Branch prediction • Predication CPU Mem I/O System software App App App Readings • Chapter 2.1 of MA:FSPTCM CIS 501 (Martin): Pipelining 3 Pre-Class Exercises • Question#1: you have a washer, dryer, and “folder” • Each takes 30 minutes per load • How long for one load in total? • How long for two loads of laundry? • How long for 100 loads of laundry? • Question #2: now assume: • Washing takes 30 minutes, drying 60 minutes, and folding 15 min • How long for one load in total? • How long for two loads of laundry? • How long for 100 loads of laundry? CIS 371 (Martin): Pipelining 4

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Pre-Class Exercises Answers • Question#1: you have a washer, dryer, and “folder” • Each takes 30 minutes per load • How long for one load in total? 90 minutes • How long for two loads of laundry? 90 + 30 = 120 minutes • How long for 100 loads of laundry? 90 + 30*99 = 3060 min • Question #2: now assume: • Washing takes 30 minutes, drying 60 minutes, and folding 15 min • How long for one load in total? 105 minutes • How long for two loads of laundry? 105 + 60 = 165 minutes • How long for 100 loads of laundry? 105 + 60*99 = 6045 min CIS 371 (Martin): Pipelining 5 Datapath Background CIS 501 (Martin): Pipelining 6 CIS 501 (Martin): Pipelining 7 Recall: The Sequential Model • Basic structure of all modern ISAs • Processor logically executes loop at left Program order : total order on dynamic insns • Order and named storage define computation • Convenient feature: program counter (PC) Insn itself at memory[PC] • Next PC is PC++ unless insn says otherwise Atomic : insn X finishes before insn X+1 starts • Can break this constraint physically (pipelining) • But must maintain illusion to preserve programmer sanity Fetch PC Decode Read Inputs Execute Write Output Next PC CIS 501 (Martin): Pipelining 8 Datapath and Control Datapath : implements execute portion of fetch/exec. loop Functional units (ALUs), registers, memory interface Control : implements decode portion of fetch/execute loop Mux selectors, write enable signals regulate flow of data in datapath Part of decode involves translating insn opcode into control signals PC I\$ Register File s1 s2 d D\$ + 4 control
CIS 501 (Martin): Pipelining 9 Single-Cycle Datapath Single-cycle datapath : true “atomic” fetch/execute loop Fetch, decode, execute one complete instruction every cycle “Hardwired control” : opcode decoded to control signals directly

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04_pipeline - This Unit(Scalar In-Order Pipelining App App...

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