makefile - Introduction Introduction • • • • make...

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Unformatted text preview: Introduction Introduction • • • • make is a UNIX utility for building projects that are comprised of make multiple source files make takes care of dependencies, and will rebuild the project if one make or more file is modified a file, usually named makefile, contains details of the dependencies, file, and therefore tells make how to build the project and Before we go to details and sample make file it will be beneficial to Before know about how .exe files are created by compilers know How .exe file is created? How Source File Revise Code Compile Success New Obj other obj Load File Loader places load file to mem Failed List errors Correct Errors Linker Links the objects .exe file in memory Dependency Notation Dependency • Target depends on source. If source has changed, execute the Target command target: source [source2] command [command] [command] • There are no source files specified, execute command There unconditionally unconditionally target: command [command] [command] Dependencies Example Dependencies • For example, a makefile to build the executable For file one from the C/C++ source files one.cpp, two.cpp and three.cpp one one.o one.c // Dependencies // one.h one.h two two.o two.c two two.o two.h three three.o three.c three three.o three.h example Makefile example one: one.o two.o three.o one: g++ -o one one.o two.o three.o g++ one.o: one.cpp one.h g++ -c one.cpp g++ two.o: two.c two.h g++ -c two.cpp g++ three.o: three.cpp three.h g++ -c three.cpp g++ What makefiles contain • Makefiles may contain the following five parts – – – – – Explicit Rules Implicit Rules Variable Definitions Directives Comments Comments What makefiles contain • Explicit Rules say when and how to remake one or more files, or the targets. It lists the other files that targets depend on, and may also give commands to use to create or update the targets. or • Implicit Rules say when and how to remake a class of files based on their names. It describes how a target may depend on a file with a name similar to the target and gives commands to create or update such target gives What makefiles contain • Variable Definitions are lines that specify a text string value for a variable that can be substituted in the text later. • Directives are commands for make to do something special while reading the makefile. These include while – – – Reading another makefile Deciding whether to use or ignore a part of the makefile Defining variable from a verbatim string containing multiple lines • Comments start with # in a line of a makefile. The rest of the line after this # are ignored. Default make Rules • make has default rules - e.g. the default rule for making make a .o file from a .c file is $(CC) $(CFLAGS) -c file.c $(CC) • the macros $(CFLAGS) and $(CC) are predefined by the make make Note • The name for the make file should be The makefile or Makefile makefile • Put comments. Comment sign is # For example: # This is makefile project3 • In the command line , you must put a TAB at the In beginning of the line. Otherwise you’ll get an error message. Note also that if you copy a makefile, copying usually destroys the tab and replaces it with spaces. You must replace the spaces with a tab on all action lines. lines. Notes • Clean the object (.o) files For example: clean: rm -f *.o rm If this is at the end of the makefile, use the command If make clean to cause it to execute ...
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