Lec03a - COMP 4300 Computer Architecture Instruction Set...

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1 COMP 4300 Computer Architecture Instruction Set (cont.) Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu Fall, 2010
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2 Operand Locations in Four ISA Classes GPR
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3 Code Sequence C = A + B Code Sequence C = A + B for Four Instruction Sets for Four Instruction Sets Stack Accumulator Register (register-memory) Register (load- store) Push A Push B Add Pop C Load A Add B Store C Load R1, A Add R1, B Store R1, C Load R1,A Load R2, B Add R3, R1, R2 Store R3, C memory memory acc = acc + mem[C] R1 = R1 + mem[C] R3 = R1 + R2
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4 General Purpose Registers (GPR) Why GPRs Dominate? Registers are much faster than memory (even cache) Register values are available immediately When memory isn’t ready, processor must wait (“stall”) Registers are convenient for variable storage Compiler assigns some variables just to registers More compact code since small fields specify registers (compared to memory addresses) Registers Cache Memory Processor Disk
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Lec03a - COMP 4300 Computer Architecture Instruction Set...

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