Lec05b - 1 COMP 4300 Computer Architecture 1. Single-Cycle...

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Unformatted text preview: 1 COMP 4300 Computer Architecture 1. Single-Cycle Datapath 2. Control Unit Design Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin [email protected] Fall, 2010 2 Datapath Components for MIPS beq beq $R1, $R2, -100 if $R1==$R2 then PC = PC+4+4*(-100) else PC = PC+4 ReadRegister#1 ReadRegister#2 WriteRegister Data Port#1 Port#2 REGISTERS Instruction Memory P C address Inst. R1 R2-100 beq ROM 16 SIGN-EXTEND 16 32 ALU zero ADD SHIFT LEFT 2 32 32 3 Datapath Connections for MIPS beq beq $R1, $R2, -100 if $R1==$R2 then PC = PC+4+4*(-100) else PC = PC+4 ReadRegister#1 ReadRegister#2 WriteRegister Data Port#1 Port#2 REGISTERS Instruction Memory P C address Inst. R1 R2-100 beq ROM 16 SIGN-EXTEND 16 32 ALU zero ADD SHIFT LEFT 2 32 32 PC+4 To branch Control 4 Complete Single-Cycle Datapath 5 5 16 RD1 RD2 RN1 RN2 WN WD RegWrite Register File Operation ALU 3 E X T N D 16 32 Z ero RD WD MemRead Data Memory ADDR MemWrite 5 Instruction 32 M U X ALUSrc MemtoReg ADD <<2 RD Instruction Memory ADDR PC 4 ADD ADD M U X M U X PCSrc 5 5 5 16 RD1 RD2 RN1 RN2 WN WD RegWrite Register File Operation ALU 3 E X T N D 16 32 Z ero RD WD MemRead Data Memory ADDR MemWrite 5 Instruction 32 M U X ALUSrc MemtoReg ADD <<2 RD Instruction Memory ADDR PC 4 ADD ADD M U X M U X PCSrc Complete Datapath Executing add add rd, rs, rt 6 5 5 16 RD1 RD2 RN1 RN2 WN WD RegWrite Register File Operation ALU 3 E X T N D 16 32 Z ero RD WD MemRead Data Memory ADDR MemWrite 5 Instruction 32 M U X ALUSrc MemtoReg ADD <<2 RD Instruction Memory ADDR PC 4 ADD ADD M U X M U X PCSrc Complete Datapath Executing load lw rt,offset(rs) 7 5 5 16 RD1 RD2 RN1 RN2 WN WD RegWrite...
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This note was uploaded on 12/07/2011 for the course COMP 3400 taught by Professor Staff during the Fall '10 term at Auburn University.

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Lec05b - 1 COMP 4300 Computer Architecture 1. Single-Cycle...

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