Lec06c - COMP 4300 Computer Architecture Pipeline Introduction Dr Xiao Qin Auburn University http/www.eng.auburn.edu/~xqin [email protected] Fall

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1 COMP 4300 Computer Architecture Pipeline: Introduction Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin [email protected] Fall, 2010
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2 Full Multicycle Implementation ALU Control Control Unit 6 6 op I[31:26] funct I[5:0] ALUOp 2 5 5 RD1 RD2 RN1 RN2 WN WD RegWrite Registers Operation ALU 3 E X T N D 16 32 Zero RD WD MemRead Memory ADDR MemWrite 5 Instruction I 32 ALUSrcB <<2 PC 4 RegDst 5 I R M D R M U X 0 1 2 3 M U X 1 0 M U X 0 1 A B ALU OUT 0 1 2 M U X <<2 CONCAT 28 32 M U X 0 1 ALUSrcA jmpaddr I[25:0] rd MUX 0 1 rt rs immediate PCSource MemtoReg IorD PCWriteCond PCWrite Zero IRWrite
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3 What is Pipelining? A way of speeding up execution of instructions Key idea : overlap execution of multiple instructions
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4 The Laundry Analogy Anna, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold Washer takes 30 minutes Dryer takes 30 minutes “Folder” takes 30 minutes “Stasher” takes 30 minutes to put clothes into drawers A B C D
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If we do laundry sequentially. .. 30
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This note was uploaded on 12/07/2011 for the course COMP 3400 taught by Professor Staff during the Fall '10 term at Auburn University.

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Lec06c - COMP 4300 Computer Architecture Pipeline Introduction Dr Xiao Qin Auburn University http/www.eng.auburn.edu/~xqin [email protected] Fall

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