Lec07a - 1 COMP 4300 Computer Architecture Pipeline:...

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Unformatted text preview: 1 COMP 4300 Computer Architecture Pipeline: Speedup Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu Fall, 2010 2 Pipeline example: lw WB Can you find a problem? 3 Basic Pipelined Processor (lw) 4 Single-Cycle vs. Pipelined Execution Non-Pipelined 200 4 00 600 800 1000 1200 14 00 1600 1800 lw $1, 100($0) Instruction Fetch REG RD ALU REG WR MEM lw $2, 200($0) Instruction Fetch REG RD ALU REG WR MEM lw $3, 300($0) Instruction Fetch Time Instruction Order 800ps 800ps 800ps Pipelined 200 4 00 600 800 1000 1200 14 00 1600 lw $1, 100($0) Instruction Fetch REG RD ALU REG WR MEM lw $2, 200($0) lw $3, 300($0) Time Instruction Order 200ps Instruction Fetch REG RD ALU REG WR MEM Instruction Fetch REG RD ALU REG WR MEM 200ps 200ps 200ps 200ps 200ps 200ps 5 Speedup Consider the unpipelined processor introduced previously. Assume that it has a 1 ns clock cycle and it uses 4 cycles for ALU operations and branches , and 5 cycles for memory operations , assume that the relative frequencies of these operations are 40%, 20%, and 40%, respectively. Suppose that due to clock skew and setup, pipelining the processor adds 0.2ns of overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from a pipeline? Average instruction execution time = 1 ns * ((40% + 20%)*4 + 40%*5) = 4.4ns Speedup from pipeline = Average instruction time unpiplined/Average instruction time pipelined = 4.4ns/1.2ns = 3.7 6 Comments about Pipelining The good news Multiple instructions are being processed at same time This works because stages are isolated by registers...
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This note was uploaded on 12/07/2011 for the course COMP 3400 taught by Professor Staff during the Fall '10 term at Auburn University.

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Lec07a - 1 COMP 4300 Computer Architecture Pipeline:...

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