Lec07c - COMP 4300 Computer Architecture Data Hazards...

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1 COMP 4300 Computer Architecture Data Hazards Control Hazards Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu Fall, 2010
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2 Review: Structural Hazards Attempt to use same resource twice at same time Example: Single Memory for instructions, data Accessed by IF stage Accessed at same time by MEM stage Solutions ? Delay second access by one clock cycle Provide separate memories for instructions, data This is what the book does This is called a “ Harvard Architecture Real pipelined processors have separate caches
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3 Data Hazards Data hazards occur when data is used before it is stored IM Reg IM Reg CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 Time (in clock cycles) sub $2 , $1, $3 Program execution order (in instructions) and $12, $2 , $5 IM Reg DM Reg IM DM Reg IM DM Reg CC 7 CC 8 CC 9 10 10 10 10 10/– 20 – 20 – 20 – 20 – 20 or $13, $6, $2 add $14, $2 , $2 sw $15, 100 ($2) Value of register $2: DM Reg Reg Reg Reg DM The use of the result of the SUB instruction in the next three instructions causes a data hazard, since the register is not written until after those instructions read it.
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4 Data Hazards Read After Write (RAW) Instr J tries to read operand before Instr I writes it Caused by a “ Dependence ” (in compiler nomenclature). This hazard results from an actual need for communication. Execution Order is: Instr I Instr J I: add r1 ,r2,r3 J: sub r4, r1 ,r3
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5 Data Hazards Write After Read (WAR ) Instr J tries to write operand before Instr I reads i Gets wrong operand Called an “ anti-dependence ” by compiler writers. This results from reuse of the name “ r1 ”. Can’t happen in MIPS 5 stage pipeline because: Execution Order is: Instr I Instr J I: sub r4, r1 ,r3 J: add r1 ,r2,r3 K: mul r6,r1,r7 All instructions take 5 stages, and Reads are always in stage 2, and Writes are always in stage 5
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6 Data Hazards Write After Write (WAW) Instr J tries to write operand before Instr I writes it
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Lec07c - COMP 4300 Computer Architecture Data Hazards...

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