Lec08a - COMP 4300 Computer Architecture Pipeline: Branch...

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1 COMP 4300 Computer Architecture Pipeline: Branch Prediction Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu Fall, 2010
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2 Review: Data Hazards Data hazards occur when data is used before it is stored IM Reg IM Reg CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 Time (in clock cycles) sub $2 , $1, $3 Program execution order (in instructions) and $12, $2 , $5 IM Reg DM Reg IM DM Reg IM DM Reg CC 7 CC 8 CC 9 10 10 10 10 10/– 20 – 20 – 20 – 20 – 20 or $13, $6, $2 add $14, $2 , $2 sw $15, 100 ($2) Value of register $2: DM Reg Reg Reg Reg DM The use of the result of the SUB instruction in the next three instructions causes a data hazard, since the register is not written until after those instructions read it.
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3 Control Hazard on Branches Review: Control Hazards 10: beq r1,r3,36 14: and r2,r3,r5 18: or r6,r1,r7 22: add r8,r1,r9 36: xor r10,r1,r11 Reg ALU DMem Ifetch Reg Reg DMem Ifetch Reg Reg DMem Ifetch Reg Reg DMem Ifetch Reg Reg DMem Ifetch Reg The penalty when branch take is _________ 3 cycles! Three Stage Stall
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4 Reducing Branch Delay Move following to ID stage a) Branch-target address calculation b) Branch condition decision Reduced penalty (1 cycle) when branch take!
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5 Control Hazard Solutions Stall stop loading instructions until result is available Predict assume an outcome and continue fetching (undo if prediction is wrong) lose cycles only on mis-predict Delayed branch specify in architecture that following instruction is always executed
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6 Branch Behavior in Programs
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This note was uploaded on 12/07/2011 for the course COMP 3400 taught by Professor Staff during the Fall '10 term at Auburn University.

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Lec08a - COMP 4300 Computer Architecture Pipeline: Branch...

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