Lec09c - COMP 4300 Computer Architecture Control for...

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1 COMP 4300 Computer Architecture Control for Pipelined Datapath Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin [email protected] Fall, 2010
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2 Pipelining in MIPS MIPS architecture was designed to be pipelined Simple instruction format (makes IF, ID easy) Single-word instructions Small number of instruction formats Common fields in same place (e.g., rs, rt) in different formats Memory operations only in lw, sw instructions (simplifies EX) Memory operands aligned in memory (simplifies MEM) Single value for writeback (limits forwarding) Pipelining is harder in CISC architectures
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3 Complete Single-Cycle Datapath Control signals shown in blue 5 5 16 RD1 RD2 RN1 RN2 WN WD RegWrite Register File Operation ALU 3 E X T N D 16 32 Zero RD WD MemRead Data Memory ADDR MemWrite 5 Instruction I 32 M U X ALUSrc MemtoReg ADD <<2 RD Instruction Memory ADDR PC 4 ADD ADD M U X M U X PCSrc MUX RegDst 5 rd I[15:11] rt I[20:16] rs I[25:21] immediate/ offset I[15:0] 0 1 0 1 1 0 1 0
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4 Pipelined Datapath with Control Signals MemtoReg 5 RD1 RD2 RN1 RN2 WN WD Register File ALU E X T N D 16 32 RD WD Data Memory ADDR 32 <<2 RD Instruction Memory ADDR PC 4 ADD ADD 5 5 5 IF/ID ID/EX EX/MEM MEM/WB Zero 0 1 MemRead ALUSrc MemWrite ALU Control 6 ALUOp 0 1 RegDst 5 rs rt rt rd RegWrite immed Branch 0 1 PCSrc PCSrc 0 1 In which stage should we place a control unit?
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5 5 5 16 RD1 RD2 RN1 RN2 WN WD RegWrite Register File Operation ALU 3 E X T N D 16 32 Zero RD WD MemRead Data Memory ADDR MemWrite 5 Instruction I 32 M U X ALUSrc MemtoReg ADD <<2 RD Instruction Memory ADDR PC 4 ADD ADD M U X M U X PCSrc MUX RegDst 5 rd I[15:11] rt I[20:16] rs I[25:21] immediate/ offset I[15:0] 0 1 0 1
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