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# Lec10a - COMP 4300 Computer Architecture Instruction-level...

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1 COMP 4300 Computer Architecture Instruction-level parallelism: Introduction Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin [email protected] Fall, 2010

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2 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8. L: SW R3, 50(R1) Assuming that there is no forwarding, zero testing is being resolved during ID , and registers can be written in the first of the WB cycle and also be read in the send half of the same WB cycle, Question: identify the resources of various hazards in the above code sequence.
3 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8. L: SW R3, 50(R1) Assuming that there is no forwarding, zero testing is being resolved during ID , and registers can be written in the first of the WB cycle and also be read in the send half of the same WB cycle, Question: identify the resources of various hazards in the above code sequence.

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4 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R6) 6. LW R5, 200(R6) 7. SUB R3, R4, R5 8. L: SW R3, 50(R1) Use compiler techniques to reshuffle/rewrite the code (without changing the meaning of the program) as to minimize data hazards as far as possible. Assume that no other general purpose registers other than those used in the code, are available.
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