Lec10b-Lab3(1)

Lec10b-Lab3(1) - COMP 4300 Computer Architecture Laboratory...

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1 COMP 4300 Computer Architecture Laboratory Assignment 3: Pipelined Datapath with Interlocks and Forwarding Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu Fall, 2010
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2 Introduction From your multi-cycle machine to a machine with pipelined datapath Based on the five stage MIPS pipeline You are allowed to create your own pipeline
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3 Introduction (cont.) Implementation of branch or load delay slots is NOT required. Implement each part as described Answer all related questions Submit your programs. You must test (i.e., compile and run) your simulator on a Linux machine .
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4 Your Pipeline A load-store GPR-based 3-operand machine Execute the subset of MIPS instructions Implement interlocks between pipe stages to recognize and resolve data hazards: through forwarding when feasible, including forwarding through the register file through NOP s otherwise (interlocks)
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5 Hazard Detection Situations LD R1 , 45(R2) DADD R5, R1 , R7 (Requires stall) LD R1 , 45(R2) DADD R5, R6, R7 DSUB R8, R1 , R7 (Requires forwarding) Comparators detect the use of R1 in the DADD and stall the DADD (and future instructions)
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Lec10b-Lab3(1) - COMP 4300 Computer Architecture Laboratory...

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