Lec13b - COMP 4300 Computer Architecture Instruction-level...

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1 COMP 4300 Computer Architecture Instruction-level parallelism: Tomasulo Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin [email protected] Fall, 2010
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2 Techniques to deal with data hazards in instruction pipelines by: Result forwarding to reduce or eliminate RAW hazards Hazard detection hardware to stall the pipeline during hazards Compiler-based static scheduling to separate the dependent instructions minimizing actual hazard- prevention stalls in scheduled code. Uses a hardware-based mechanism to rearrange instruction execution order to reduce stalls dynamically at runtime ( dynamic scheduling ) Better dynamic exploitation of instruction-level parallelism (ILP) We learned scoreboard techniques We will learn another technique Tomasulo next. Review: Scoreboard
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The amount of parallelism available among the instructions (chosen from the same basic block) The number of score entries (The size of the scoreboard determines the size of the window) The number and types of functional units (Structural hazards increase when dynamic scheduling is used) The presence of antidependence and output
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This note was uploaded on 12/07/2011 for the course COMP 3400 taught by Professor Staff during the Fall '10 term at Auburn University.

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Lec13b - COMP 4300 Computer Architecture Instruction-level...

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