Lec16a - Memory Hierarchy: Introduction Dr. Xiao Qin Auburn...

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1 Memory Hierarchy: Introduction Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin xqin@auburn.edu Fall, 2010
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2 Memory Systems - the Big Picture Memory provides processor with Instructions Data Problem: Control Datapath Memory Processor Input Output Instructions Data Five Classics Components” Picture memory is too slow and too small
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3 DRAM Year Size Cycle Time 1980 64 Kb 250 ns 1983 256 Kb 220 ns 1986 1 Mb 190 ns 1989 4 Mb 165 ns 1992 16 Mb 145 ns 1995 64 Mb 120 ns CapacitySpeed (latency) Logic: 2x in 3 years 2x in 3 years DRAM: 4x in 3 years 2x in 10 years Disk: 4x in 3 years 2x in 10 years 1000:1! 2:1! Technology Trends
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4 µProc 60%/yr. (2X/1.5yr) DRAM 9%/yr. (2X/10 yrs) 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (grows 50% / year) Performance Time “Moore’s Law” Processor-DRAM Memory Gap (latency) Why Cares About Memory Hierarchy?
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5 Memory Hierarchy - the Big Picture Problem: memory is too slow and too small Solution: memory hierarchy Control Datapath Secondary Storage (Disk) Processor R e g i s t r L2 Off-Chip Cache Main Memory (DRAM) L 1 O n - C h p a c 0.5-25 5,000,000 (5ms) Speed (ns): 80-250 <1K Size (bytes): >100G <16G <16M 0.25-0.5
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6 Memory Configuration in Current PCs Processor System Controller L1 Cache Main Memory (DRAM) L2/L3 Cache (SRAM) (I/O Bus) Static RAM (SRAM) - used for L1, L2 cache Fast - 0.5-25ns access time (less for on-chip) Larger, More Expensive Higher power consumption Dynamic RAM (DRAM) - used for PC main memory Slower - 80-250ns access time* Smaller, Cheaper Lower power consumption
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7 System Components SDRAM PC100/PC133 100-133MHz 64-128 bits wide 2-way inteleaved ~ 900 MBYTES/SEC )64bit) Double Date Rate (DDR) SDRAM PC3200 200 MHz DDR 64-128 bits wide 4-way interleaved ~3.2 GBYTES/SEC (64bit) DDR2 SDRAM 667MHZ 8~16 bit wide CPU Caches System Bus I/O Devices Memory I/O Controllers Bus Adapter Disks Displays Keyboards Networks NICs Main I/O Bus Memory Controller Example: PCI, 33-66MHz 32-64 bits wide 133-528 MB/s PCI-X 133MHz 64-bits wide 1066 MB/s CPU Core 1 GHz - 3.6 GHz 4-way Superscaler RISC or RISC-core (x86): Deep Instruction Pipelines Dynamic scheduling Multiple FP, integer FUs
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This note was uploaded on 12/07/2011 for the course COMP 3400 taught by Professor Staff during the Fall '10 term at Auburn University.

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Lec16a - Memory Hierarchy: Introduction Dr. Xiao Qin Auburn...

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