Lec17-review - 1 COMP 4300 Computer Architecture Review for...

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Unformatted text preview: 1 COMP 4300 Computer Architecture Review for Final Exam Dr. Xiao Qin Auburn University http://www.eng.auburn.edu/~xqin [email protected] Fall, 2010 2 Final Exam Review Focus on materials after the midterm, including Pipeline Exceptions Control for Pipelined Datapath Instruction Level Parallelism Scoreboard Tomasula Method Cache & Memory Design 3 Synchronous vs Asynchronous Definition : If the event occurs at the same place every time the program is executed with the same data and memory allocation, the event is synchronous . Otherwise asynchronous . Except for hardware malfunctions, asynchronous events are caused by devices external to the CPU and memory. Asynchronous events usually are easier to handled because asynchronous events can be handled after the completion of the current instruction. 4 Pipeline: Exceptions Exceptions Interrupts Traps Exceptions in five-stage pipeline Exception detection (not covered) Exception handling Stop the offending instruction Flush instructions following the offending instructions Save the address of the offending instruction, and Jump to a prearranged exception handler code 5 Pipelining in MIPS MIPS architecture was designed to be pipelined Simple instruction format (makes IF, ID easy) Single-word instructions Small number of instruction formats Common fields in same place (e.g., rs, rt) in different formats Memory operations only in lw, sw instructions (simplifies EX) Memory operands aligned in memory (simplifies MEM) Single value for writeback (limits forwarding) Pipelining is harder in CISC architectures 6 Adding Control Basic approach: build on single-cycle control Place control unit in ID stage Pass control signals to following stages Later: extra features to deal with: Data forwarding Stalls Exceptions 7 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8. L: SW R3, 50(R1) Assuming that there is no forwarding, zero testing is being resolved during ID , and registers can be written in the first of the WB cycle and also be read in the send half of the same WB cycle, Question: identify the resources of various hazards in the above code sequence. 8 Class Exercise Consider the following code segment 1. LW R1, 0(R4) 2. LW R2, 0(R5) 3. ADD R3, R1, R2 4. BNZ R3, L 5. LW R4, 100(R1) 6. LW R5, 100(R2) 7. SUB R3, R4, R5 8. L: SW R3, 50(R1) Assuming that there is no forwarding,...
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This note was uploaded on 12/07/2011 for the course COMP 3400 taught by Professor Staff during the Fall '10 term at Auburn University.

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Lec17-review - 1 COMP 4300 Computer Architecture Review for...

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