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02-arch-support

02-arch-support - Architectural Support for Operating...

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Architectural Support for Operating Systems Prof. Sirer CS 4410 Cornell University
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Basic Computer Organization CPU Memory ?
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Keyboard Let’s build a keyboard Lots of mechanical switches Need to convert to a compact form (binary) We’ll use a special mechanical switch that, when pressed, connects two wires simultaneously
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Keyboard When a key is pressed, a 7-bit key identifier is computed + 3-bit encoder (4 to 3) 4-bit encoder (16 to 4) not all 16 wires are shown
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Keyboard A latch can store the keystroke indefinitely + 3-bit encoder (4 to 3) 4-bit encoder (16 to 4) not all 16 wires are shown Latch
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Keyboard The keyboard can then appear to the CPU as if it is a special memory address + 3-bit encoder (4 to 3) 4-bit encoder (16 to 4) not all 16 wires are shown Latch CPU
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Device Interfacing Techniques Memory-mapped I/O Device communication goes over the memory bus Reads/Writes to special addresses are converted into I/O operations by dedicated device hardware Each device appears as if it is part of the memory address space Programmed I/O CPU has dedicated, special instructions CPU has additional input/output wires (I/O bus) Instruction specifies device and operation Memory-mapped I/O is the predominant device interfacing technique in use
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Polling vs. Interrupts In our design, the CPU constantly needs to read the keyboard latch memory location to see if a key is pressed Called polling Inefficient An alternative is to add extra circuitry so the keyboard can alert the CPU when there is a keypress Called interrupt driven I/O Interrupt driven I/O enables the CPU and devices to perform tasks concurrently, increasing throughput Only needs a tiny bit of circuitry and a few extra wires to implement the “alert” operation
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Interrupt Driven I/O CPU Memory An interrupt controller mediates between competing devices Raises an interrupt flag to get the CPU’s attention Identifies the interrupting device Can disable (aka mask) interrupts if the CPU so desires intr dev id Interrupt Controller
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Interrupt Driven I/O CPU Memory An interrupt controller mediates between competing devices Raises an interrupt flag to get the CPU’s attention Identifies the interrupting device Can disable (aka mask) interrupts if the CPU so desires intr
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Interrupt Management Interrupt controllers manage interrupts Maskable interrupts: can be turned off by the CPU for critical processing Nonmaskable interrupts: signifies serious errors (e.g.
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