lec2_yield_moore - ELEC 7770 Advanced VLSI Design Spring...

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Unformatted text preview: ELEC 7770 Advanced VLSI Design Spring 2010 VLSI Yield and Moore’s Law Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr10/course.html Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 1 VLSI Chip Yield A manufacturing defect is a finite chip area with manufacturing electrically malfunctioning circuitry caused by errors in the fabrication process. errors A chip with no manufacturing defect is called a chip good chip. good Fraction (or percentage) of good chips produced Fraction in a manufacturing process is called the yield. Yield is denoted by symbol Y. Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 2 Importance of Yield Cost of a chip = Cost of fabricating and testing a wafer Yield × Number of chip sites on the wafer Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 3 Clustered VLSI Defects Good chips Faulty chips Defects Wafer Unclustered defects Wafer yield = 12/22 = 0.55 Spring 10, Jan 13 Spring Clustered defects (VLSI) Wafer yield = 17/22 = 0.77 ELEC 7770: Advanced VLSI Design (Agrawal) 4 Yield Parameters Defect density (d ) = Average number of defects per unit chip area chip Chip area (A ) Clustering parameter (α ) Negative binomial distribution of defects, Negative p (x ) = Prob(number of defects on a chip = x ) Γ (α +x ) (Ad / α) x = . x ! Γ ( α) (1+Ad / α) α+x where Γ is the gamma function α = 0, p (x ) is a delta function (max. clustering) α = ∞ , p (x ) is Poisson distribution (no clustering) Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 5 Yield Equation Y = Prob( zero defect on a chip ) = p (0) Y = ( 1 + Ad / α ) – α Example: Ad = 1.0, α = 0.5, Y = 0.58 Unclustered defects: α = ∞ , Y = e – Ad Example: Ad = 1.0, α = ∞ , Y = 0.37 too pessimistic ! Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 6 Effect of Defect Clustering 1.00 Ad = 0.5 Yield 0.75 e-0.5 = 0.607 0.50 0.25 0.00 0 0.5 1.0 1.5 2.0 Clustering Parameter, α Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 7 0.906 0.5 0.27 Yield of 1 cm2 chip 0.913 0.1 Initial process 5.0 Mature process Clustering parameter, α Ranges of Yield Parameters 0.50 1.5 Defect density, d in defects per cm2 Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 8 References Clustered yield model M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing for M. Digital, Memory and Mixed-Signal VLSI Circuits, Springer, 2000, Digital, Springer, Chapter 3. Chapter C. H. Stapper, “On Yield, Fault Distributions, and Clustering of C. Particles,” IBM Jour. of Res. and Dev., vol. 30, no. 3, pp. 326-338, IBM ., May 1986. May The unclustered defect model was first described in paper: B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,” B. Proc. IEEE, vol. 52, no. 12, pp. 1537-1545, December 1964. Proc. A general reference on clustered distributions: A. Rogers, Statistical Analysis of Spatial Dispersions, London, United A. Statistical London, Kingdom: Pion Limited, 1974. Kingdom: Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 9 Gordon E. Moore Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 10 1965 “Cramming More Components onto Integrated Cramming Circuits,” Electronics, vol. 38, no. 8, April 19, 1965. Electronics The complexity for minimum component costs has increased at a rate of roughly a factor of two per year (see graph on next page). Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years. That means by 1975, the number of components per integrated circuit for minimum cost will be 65,000. I believe that such a large circuit can be built on a single wafer. Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 11 Moore’s 1965 Graph 1975 Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 12 1975 “Progress in Digital Integrated Electronics,” Progress IEDM Tech. Digest, 1975, pp. 11-13. IEDM . . . the rate of increase of complexity can be expected to change slope in the next few years as shown in Figure 5. The new slope might approximate a doubling every two years, rather than every year, by the end of the decade. Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 13 Figure 5 of Moore’s 1975 Paper Components per chip 16M 1M 64K 4K 256 16 1 60 65 70 75 80 85 Year Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 14 1995 “Lithography and the Future of Moore’s Law,” Lithography Proc. SPIE, vol. 2437, May 1995. Proc. By making things smaller, everything gets better simultaneously. There is little need for trade-offs. The speed of our products goes up, the power consumption goes down, system reliability, as we put more of the system on a chip, improves by leaps and bounds, but especially the cost of doing thing electronically drops as a result of the technology. (SPIE – Society of Photonic Instrumentation Engineers) Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 15 Also in the 1995 Paper . . . I have no idea what will happen beyond 0.18 microns. In fact, I still have trouble believing we are going to be comfortable at 0.18 microns using conventional optical systems. Beyond this level, I do not see any way that conventional optics carries us any further. Of course, some of us said this about the one micron level. This time, however, I think there are fundamental materials issues that will force a different direction. The people at this conference are going to have to come up with something new to keep us on the long term trend. Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 16 Source: Wikipedia Moore’s Law Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 17 2010 Problems with technology: High power consumption Power density Leakage Process variation – larger as a fraction of feature size Increased noise sensitivity Problems with design: Verification of correctness – logic and timing Ensuring reliable operation Testing Spring 10, Jan 13 Spring ELEC 7770: Advanced VLSI Design (Agrawal) 18 ...
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This note was uploaded on 09/16/2011 for the course ELEC 7770 taught by Professor Agrawal,v during the Spring '08 term at Auburn University.

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