CDA3101-Fall2011-Recitation01

CDA3101-Fall2011-Recitation01 - requires 2 more clock...

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CDA 3101 Recitation Session 1
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Digital Logic 1 Prove that NAND is universal gate Represent the following gates using NAND NOT AND OR XOR (?)
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Digital Logic 2 Find the SOP (sum-of-product) representation for the following expression using truth table f = xy OR yzw AND zx OR xw
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Performance Evaluation 1 Machine M1, which clocks at 2GHz, can run a program P1 in 15 seconds, under an average CPI of 3. How many instructions are required to run P1? We want to design a machine M2 which, under the same average CPI, can run P1 in a third of the time. How fast must the clock speed of M2 be to achieve this task?
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Performance Evaluation 2 We have two machines, M1 and M2, which we will use to run a program P1. M2 runs at twice the clock speed of M1, and
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Unformatted text preview: requires 2 more clock cycles on average per instruction. M2 runs P1 in 75% of the time it takes for M1 to run the same program – At what CPI does M1 run? M2? – If the program consists of 5000 instructions, and M1 can run it in ten seconds, what is the clock speed of M2? Performance Evaluation 3 • Given a machine M1 with clock rate 4 GHz and a program P2 that has 50,000 instructions and the following instruction mix and CPI, Instruction Type % Incidence CPI -----------------+--------------+------ A | 12 | 6 B | 25 | 13 C | y | 11 D | 23 | 5 E | rem | 2 what incidence percentage (%y) should instructions of type C have to guarantee that the execution time is no more than 100 micro-seconds?...
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This note was uploaded on 12/10/2011 for the course CDA 3101 taught by Professor Small during the Fall '08 term at University of Florida.

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CDA3101-Fall2011-Recitation01 - requires 2 more clock...

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