CDA3101-L17-processor-datapath

CDA3101-L17-processor-datapath - CDA 3101 Fall 2011...

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CDA 3101 Fall 2011 Introduction to Computer Organization Processor Organization Datapath Design 10-12 October 2011
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Review Construction of the ALU Building blocks (digital design gates) Modular design Multiplexor chooses operation All operations are performed in parallel Carry lookahead adder Computer arithmetic Finite precision Laws of algebra do not always hold Integers: two’s complement representation Floating point: IEEE 754 standard
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Overview Computer organization (microarchitecture) Processor organization Datapath Control Register file Processor implementation overview Clocking methodologies Sequential circuits Latches Registers
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Processor Performance Program Compiler ISA Microarchitecture Hardware CPU time = IC * CPI * Cycle time
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Computer Organization I/O device I/O device I/O Subsystem Processor Memory Subsystem . . . Address Bus Data Bus Control Bus
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The Processor Processor ( CPU ) Active part of the computer Does all the work Data manipulation Decision-making Datapath Hardware that perform all required operations ALU + registers + internal buses The brawn Control Hardware which tells the datapath what needs to be done The brain
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Processor Organization ALU Control Unit Registers Control signals Data values Control signals Control bus signals Data values (results) Data values (operands) Address bus Data bus
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Implementation of MIPS ISA determines many aspects of implementation
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This note was uploaded on 12/10/2011 for the course CDA 3101 taught by Professor Small during the Fall '08 term at University of Florida.

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CDA3101-L17-processor-datapath - CDA 3101 Fall 2011...

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