PLA ROM - Lecture 10 Read-only memories (ROMs) PLDs Two...

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1 Lecture 10 s PLDs r ROMs s Multilevel logic 2 Read-only memories (ROMs) s Two dimensional array of stored 1s and 0s r Input is an address ROM decodes all possible input addresses r Stored row entry is called a "word" r ROM output is the decoded word 3 ROMs inputs outputs n address lines 2 n word lines decoder • • • • • • memory array (2 n words by m bits) 4 Like this PLA example F1 = ABC F2 = A + B + C F3 = A' B' C' F4 = A' + B' + C' F5 = A xor B xor C A'B'C' A'B'C A'BC' A'BC AB'C' AB'C ABC' ABC A B C F1 F2 F3 F4 F5 Think of as a memory-address decoder Memory bits 0 1 0 0 1 0 1 1 A B C F1 F2 F3 F4 F5 0 0 0 0 0 1 1 0 0 0 1 0 1 0 1 1 0 1 0 0 1 0 1 1 0 1 1 0 1 0 1 0 1 0 0 0 1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0 0 1 5 ROM details s Similar to a PLA but with a fully decoded and fixed AND array s Completely flexible OR array (unlike a PAL) 6 ROM details decoder n-1 0 Address 2 n-1 0 +5V Bit lines : Normally pulled high through resistor. If bit stores a zero, then transistor pulls low when row is selected. 1 2 Only one word line is active at any time m-1 0 Outputs
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7 Two-level logic using a ROM s Use a ROM to directly store a truth table r No need to minimize logic A B C F0 F1 F2 F3 0 0 0 0 0 1 0 0 0 1 1 1 1 0 0 1 0 0 1 0 0 0 1 1 0 0 0 1 1 0 0 1 0 1 1 1 0 1 1 0 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 0 ROM 8 words x 4 bits/word address outputs A B C F 0 F 1 F 2 F 3 You specify whether to store 1 or 0 in each location in the ROM 8 ROMs versus PLAs/PALs ROMs: s Benefits
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This note was uploaded on 12/10/2011 for the course ECE 200 taught by Professor Nasis during the Spring '08 term at Drexel.

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PLA ROM - Lecture 10 Read-only memories (ROMs) PLDs Two...

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