Soc_Verification - SoC Verification Methodology Prof...

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1 SoC Verification Methodology Prof. Chien-Nan Liu TEL: 03-4227151 ext:4534 Email: [email protected]
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2 Outline l Verification Overview l Verification Strategies l Tools for Verification l SoC Verification Flow
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3 What is Verification ? l A process used to demonstrate the functional correctness of a design l To making sure your are verifying that you are indeed implementing what you want l To ensure that the result of some transformation is as expected Specification Netlist Transformation Verification Source : “Writing Test Benches – Functional Verification of HDL Models” by Janick Bergeron, KAP, 2000.
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4 Verification Problems l Was the spec correct ? l Did the design team understand the spec? l Was the blocks implemented correctly? l Were the interfaces between the blocks correct? l Does it implement the desired functionality? l ……
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5 Testing v.s. Verification l Testing verifies manufacturing Verify that the design was manufactured correctly Specification Netlist Silicon HW Design Verification Manufacturing Testing Source : “Writing Test Benches – Functional Verification of HDL Models” by Janick Bergeron, KAP, 2000.
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6 SoC Design Verification l Using pre-defined and pre-verified building block can effectively reduce the productivity gap Block (IP) based design approach Platform based design approach l But 60 % to 80 % of design effort is now dedicated to verification
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7 Verification Design High Level Design RTL and Block Test Synthesis Timing Analysis DFT Extended Simulation Equivalence Checking Emulation Support Emulation Software System Simulation ASIC Testbenches BEH Model Source : “Functional Verification on Large ASICs” by Adrian Evans, etc., 35th DAC, June 1998. An Industrial Example Bottleneck !!
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8 Verification Complexity l For a single flip-flop: Number of states = 2 Number of test patterns required = 4 l For a Z80 microprocessor (~5K gates) Has 208 register bits and 13 primary inputs Possible state transitions = 2 bits+inputs = 2 221 At 1M IPS would take 10 53 years to simulate all transitions l For a chip with 20M gates ?????? *IPS = Instruction Per Second
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9 When is Verification Complete ? l Some answers from real designers: When we run out of time or money When we need to ship the product When we have exercised each line of the HDL code When we have tested for a week and not found a new bug We have no idea!! l Designs are often too complex to ensure full functional coverage The number of possible vectors greatly exceeds the time available for test
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10 Typical Verification Experience Functional testing Weeks B u g s p e r w e e k Tapeout Purgatory
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11 Error-Free Design ? l As the number of errors left to be found decreases, the time and cost to identify them increases l Verification can only show the presence of errors, not their absence l Two important questions to be solved: How much is enough?
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