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Unformatted text preview: LSU EE 4720 Dynamic Scheduling Study Guide Fall 2005 David M. Koppelman 1.1 Introduction The material on dynamic scheduling is not covered in detail in the text, which is unfortunate since as of this writing most general-purpose processors are dynamically scheduled. This study guide provides a summary of dynamic scheduling and a guide to sample problems from old homeworks and exams. (The solutions are sometimes detailed and so are a valuable study resource.) In a statically scheduled processor instructions start execution in program order while in a dynamically scheduled processor instructions can start execution out of order. Statically scheduled systems are much simpler since instructions march through the pipeline in step, with bubbles (gaps) inserted where necessary. A shortcoming is that an instruction that must wait, say for an operand, blocks all of the instructions ahead of it (towards IF). Those instructions with dependencies on the waiting instruction would have to wait anyway but there is no reason to block other instructions (other than hardware cost). In a dynamically scheduled system the only instructions that normally must wait are those for which input operands are not ready. (There are other reasons for waiting, for example, the needed functional unit is busy.) Dynamically scheduled processors are far more costly but achieve better performance than static scheduling on superscalar processors, especially when loads miss the cache (covered later) and so take more than a cycle or two. As of this writing most general-purpose processors are dynamically scheduled. This includes the Pentium III and Pentium 4, Alpha 21264, MIPS R10000, PowerPC 620, and HP-PA 8000, and the later versions of these processors. Two exceptions are the Sun UltraSparc III and the Intel Itanium 2, which are statically scheduled. 1.2 Summary of Dynamic Scheduling Method 3 In class three methods of dynamic scheduling were mentioned, but (in Fall 2003) only one was covered in detail, Method 3. In Method 3 register values are stored in a physical register file and physical register numbers are used to re-name registers. This is the only method covered in the Fall 2003 semester and so Fall 2003 final exam questions are unlikely to use the other methods. The following is a brief description of Method 3. First, activities in each stage are covered, then the tables and other elements are described. The descriptions below refer to the following illustration: 25:21 20:16 rsPR ID:dst ID Reg. Map IR NPC +4 PC Mem Port Addr Data PC P C I D : d s t I D : S t : C , X , WB:ROB # WB:C,X Addr D In R e o r d e r B u f f e r C:dst Control Control ROB # Op, IQ Common Data Bus (CDB) ID: ROB # tail head WB C ID IF rtPR F r e e L i s t I D : d s t P R I D : d s t P R C:dstPR C Instr. Queue Addr Addr Data Data Addr D In rsPR rtPR rsVal rtVal Physical Register File Op, dstPR, ROB# Out In Scheduler Q EX dstPR dstVal....
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.
- Fall '08