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fe(1) - Name Computer Architecture EE 4720 Final...

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Unformatted text preview: Name Computer Architecture EE 4720 Final Examination 6 December 2010, 7:30–9:30 CST Alias Problem 1 (10 pts) Problem 2 (14 pts) Problem 3 (14 pts) Problem 4 (14 pts) Problem 5 (15 pts) Problem 6 (15 pts) Problem 7 (18 pts) Exam Total (100 pts) Good Luck! Problem 1: (10 pts) The diagram below shows a 5-stage pipeline that looks alot like our familiar MIPS implementation but it’s actually an implementation of ISA X . (The diagram is based on the solution to Homework 3, in which a shift unit was added to MIPS.) format
 immed
 IR
 Addr
 20:16
 9:5
 IF
 ID
 EX
 WB
 ME
 rs1v
 rs2v
 IMM
 NPC
 ALU
 Addr
 Data
 Data
 Addr
 D In
 +1
 PC
 Mem
 Port
 Addr
 Data
 Out
 Addr
 Data
 In
 Mem
 Port
 Data
 Out
 rtv
 ALU
 MD
 dst
 dst
 dst
 NPC
 =
 30
 2
 2’b0
 + 25:0
 29:26
 29:0
 0
1
 VIN
 VOUT
 sign in
 AMT
 DIR (1=left)
 s
 a
 mx
 d
 4:0
 4:0
 is Shift
 10:10
 12:12
 11:11
 31:31
 shf
 mx
 im5
 5b0
 5b31
 25:21
 31:26
 15:10
 ( a ) ISA X instruction format T encodes the shift instructions and others, it is the equivalent of format R in MIPS. Based on the diagram above show the encoding for ISA X format T. Format T encoding, including bit positions and field names. Encoding: 31 ( b ) Consider the shift instructions sll , sllv , srl , srlv , sra , and srav . Suppose that the encoding of one of these instructions is zero (meaning that every field value is zero). Show the opcode field value(s) for each of these instructions based on the diagram above. Hint: The control signal for each top mux input is 0, etc. Opcode field value(s) for: sll , sllv , srl , srlv , sra , and srav . ( c ) Explain why the implementation of instructions such as sw r1,2(r3) and beq r1, r2 TARG would be less elegant for ISA X than for MIPS. Hint: It has something to do with registers. sw and beq less elegant because... 2 Problem 2: (14 pts) Answer the questions below. ( a ) Complete the execution diagram for the MIPS code below on a two-way superscalar statically scheduled implementation of the type described in class. add r1, r2, r3 add r4, r5, r6 add r7, r4, r8 lw r9, 0(r7) addi r1, r9, 3 xor r10, r11, r12 Complete the diagram above. ( b ) Show the execution of the code below on an 8-way superscalar statically scheduled processor of the type described in class. Branches are not predicted. Find the CPI for a large number of iterations. LOOP: # Address of first insn is 0x1000 and r1, r1, r5 add r3, r3, r1 lw r1, 0(r2) bne r2, r4 LOOP addi r2, r2, 4 Complete diagram above for enough iterations to determine CPI....
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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fe(1) - Name Computer Architecture EE 4720 Final...

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