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fe(3) - Name Computer Architecture EE 4720 Final...

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Unformatted text preview: Name Computer Architecture EE 4720 Final Examination 11 May 2010, 12:30–14:30 CDT Alias Problem 1 (15 pts) Problem 2 (20 pts) Problem 3 (10 pts) Problem 4 (15 pts) Problem 5 (15 pts) Problem 6 (10 pts) Problem 7 (15 pts) Exam Total (100 pts) Good Luck! Problem 1: (15 pts) The statically scheduled MIPS implementation including the floating-point pipeline is illustrated below. format
 immed
 IR
 Addr
 25:21
 20:16
 IF
 EX
 WB
 MEM
 rsv
 rtv
 IMM
 NPC
 ALU
 Addr
 Data
 Data
 Addr
 D In
 +1
 PC
 Mem
 Port
 Addr
 Data
 Out
 Addr
 Data
 In
 Mem
 Port
 Data
 Out
 rtv
 ALU
 MD
 dst
 dst
 dst
 Decode
 dest. reg
 NPC
 Int Reg File
 FP Reg File
 fd
 fd
 WF
 Addr
 Data
 D In
 WE
 Addr
 Addr
 Data
 fsv
 ftv
 15:11
 20:16
 M6
 we
 we
 Decode
 dest. reg
 ID
 A4
 fd
 we
 fd
 we
 A3
 A2
 A1
 M3
 M4
 M5
 xw
 fd
 we
 xw
 fd
 we
 xw
 M2
 M
 1
 xw
 xw
 fd
 we
 uses FP mul
 uses FP add
 FP load
 Stall
 ID
 "0"
 "2"
 "1"
 30
 2
 "0"
 + 15:0
 29:0
 0
 1
 2
 ( a ) Consider the instruction mtc1 f2, r4 . On the diagram above show the path taken by the data on its trip from r4 to f2 . Show path taken by value using a squiggly line on the diagram above. ( b ) The control logic for the FP pipeline needs only a small change to handle mtc1 . Make that change above. (This has nothing to do with the bypass problem below.) Control logic for mtc1 in diagram above. (Ignore bypasses.) ( c ) Add the hardware needed to implement swc1 . Add only datapath, not control logic. Datapath for swc1 . 2 Problem 1, continued: # Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 lui r1, 0x4593 IF ID EX ME WB ori r1, r1, 0x819c IF ID EX ME WB mtc1 f1, r1 IF ID EX ME WF add.s f2, f2, f1 IF ID A1 A2 A3 A4 WF mtc1 f4, r4 IF ID EX ME WF sub.s f6, f4, f1 IF ID A1 A2 A3 A4 WF swc1 f6, 0(r5) IF ID -------> EX ME WF # Cycle 1 2 3 4 5 6 7 8 9 10 11 12 13 ( d ) The code fragment execution (pipeline diagram) above could not occur on the pipeline above because certain bypass paths are needed. Add those bypass paths for the code above. Show the cycle in which each added bypass path is used by the code above. ( e ) Add control logic needed to detect the bypass used from mtc1 to sub.s . The logic should deliver a signal, BYPASS , to the stage containing the bypass multiplexors. The BYPASS signal should be true if the bypass is needed....
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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fe(3) - Name Computer Architecture EE 4720 Final...

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