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Unformatted text preview: Name Computer Architecture EE 4720 Final Examination 7 May 2009, 17:3019:30 CDT Alias Problem 1 (20 pts) Problem 2 (20 pts) Problem 3 (20 pts) Problem 4 (20 pts) Problem 5 (20 pts) Exam Total (100 pts) Good Luck! Problem 1: (20 pts) The MIPS implementation below, taken from the solution to last semesters final, includes hardware to implement an exception test instruction. Several wires on the diagram are broken with heavy solid lines and marked with Fx and a value (mostly ). These indicate potential fault locations. If there is no fault the wire acts normally, if there is a fault the wire is broken at the heavy line and the free half takes on the indicated value. For example, if fault Fa is present the bottom input to the OR gate is always zero however the ID/EX.we signal on the other side is unaffected. format immed IR Addr 25:21 20:16 IF EX WB MEM rsv rtv IMM NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Data Out rtv ALU MD dst dst dst Decode dest. reg NPC Int Reg File FP Reg File fd fd WF Addr Data D In WE Addr Addr Data fsv ftv 15:11 20:16 M6 we we Decode dest. reg ID A4 fd we fd we A3 A2 A1 M3 M4 M5 xw fd we xw fd we xw M2 M 1 xw xw fd we uses FP mul uses FP add FP load Stall ID "0" "2" "1" 30 2 "0" + 15:0 29:0 0 1 2 is test e e 0 1 2 1b0 t t Changes to stall for test insn. Logic to suppress WF if exception occurs before test. Fa 0 Fb 0 Fc 1 The problem here is to detect which fault, if any, is present by running test programs. One test program, and a pipeline diagram, appears below. A handler has been set up that will set a goodException variable to 1 if register and memory values are as expected, otherwise it is set to -1. The goodException variable is initialized to 0 before each test....
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.
- Fall '08