fe - Name Computer Architecture EE 4720 Final Examination 9...

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Unformatted text preview: Name Computer Architecture EE 4720 Final Examination 9 May 2011, 15:0017:00 CDT Alias Problem 1 (20 pts) Problem 2 (10 pts) Problem 3 (20 pts) Problem 4 (20 pts) Problem 5 (30 pts) Exam Total (100 pts) Good Luck! Problem 1: (20 pts) The MIPS implementation below is similar to the one frequently used in class, except that it has bypass paths to the branch condition comparison unit. format immed IR Addr 25:21 20:16 IF ID EX WB ME rsv rtv IMM NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Out rtv ALU MD dst dst dst Decode dest. reg NPC = 30 2 2b0 + 15:0 25:0 29:26 29:0 1 15:0 Data ( a ) Show the execution of the code fragments below on the illustrated implementation up until the fetch of the first instruction of the second iteration. Be sure to account for the dependence on the branch condition. Pipeline execution diagram of code below. LOOP1: lw r1, 0(r2) addi r2, r2, 4 bneq r2, r3 LOOP1 add r4, r4, r1 Pipeline execution diagram of code below. LOOP2: lw r1, 0(r2) lw r2, 4(r2) bneq r2, r0 LOOP2 add r4, r4, r1 2 ( b ) The implementation below has hardware in IF (not shown) to predict branches. Since it has prediction hardware the branch resolution hardware (the hardware that computes the branch condition and branch target) could be moved to the ME stage. Move the branch resolution hardware. Note that the resolution hardware will be used only if the branch is mispredicted. format immed IR Addr 25:21 20:16 IF ID EX WB ME rsv rtv IMM NPC ALU Addr Data Data Addr D In +1 PC Mem Port Addr Data Out Addr Data In Mem Port Out rtv ALU MD dst dst dst Decode dest. reg NPC = 30 2 2b0 + 15:0 25:0 29:26 29:0 1 15:0 Data Move resolution hardware to the ME stage. Add any bypasses to resolution hardware needed by code samples in this problem. Cross out unused hardware in ID . 3 Problem 1, continued: Consider the implementation from the previous part. ( c ) Resolving the branch in ME with prediction can hurt performance with the code below compared to resolving in ID with prediction when the branch is hard to predict. By how much will it hurt performance?...
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fe - Name Computer Architecture EE 4720 Final Examination 9...

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