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fe_sol - Name Solution Computer Architecture EE 4720 Final...

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Unformatted text preview: Name Solution Computer Architecture EE 4720 Final Examination 6 December 2010, 7:30–9:30 CST Alias On File Problem 1 (10 pts) Problem 2 (14 pts) Problem 3 (14 pts) Problem 4 (14 pts) Problem 5 (15 pts) Problem 6 (15 pts) Problem 7 (18 pts) Exam Total (100 pts) Good Luck! Problem 1: (10 pts) The diagram below shows a 5-stage pipeline that looks alot like our familiar MIPS implementation but it’s actually an implementation of ISA X . (The diagram is based on the solution to Homework 3, in which a shift unit was added to MIPS.) format
 immed
 IR
 Addr
 20:16
 9:5
 IF
 ID
 EX
 WB
 ME
 rs1v
 rs2v
 IMM
 NPC
 ALU
 Addr
 Data
 Data
 Addr
 D In
 +1
 PC
 Mem
 Port
 Addr
 Data
 Out
 Addr
 Data
 In
 Mem
 Port
 Data
 Out
 rtv
 ALU
 MD
 dst
 dst
 dst
 NPC
 =
 30
 2
 2’b0
 + 25:0
 29:26
 29:0
 0
1
 VIN
 VOUT
 sign in
 AMT
 DIR (1=left)
 s
 a
 mx
 d
 4:0
 4:0
 is Shift
 10:10
 12:12
 11:11
 31:31
 shf
 mx
 im5
 5b0
 5b31
 25:21
 31:26
 15:10
 ( a ) ISA X instruction format T encodes the shift instructions and others, it is the equivalent of format R in MIPS. Based on the diagram above show the encoding for ISA X format T. checked Format T encoding, including bit positions and field names. Solution appears below. The source registers are named rs1 and rs2 , those names are taken from the ID/EX pipeline latches, the bit positions at the input to the register file provide their place in the instruction encoding. The input to the is Shift unit provide the location of the opcode fields. Through its connection to the shifter one finds that bits 4:0 are the equivalent of the MIPS sa field. The mux at the input to the dst pipeline latch provides the destination register field bits, 25:21 . Encoding: Opc 31 26 rd 25 21 rs1 20 16 opT 15 10 rs2 9 5 im5 4 ( b ) Consider the shift instructions sll , sllv , srl , srlv , sra , and srav . Suppose that the encoding of one of these instructions is zero (meaning that every field value is zero). Show the opcode field value(s) for each of these instructions based on the diagram above. Hint: The control signal for each top mux input is 0, etc. checked Opcode field value(s) for: sll , sllv , srl , srlv , sra , and srav . From inspection of the diagram we see that bit 10 determines whether the shift is arithmetic (signed) (bit 10 is 1 ) or logical (unsigned) (bit 10 is ). From inspection of the diagram we see that bit 11 determines whether the shift amount is obtained from the rs1 register (possibly bypassed) or if bit 11 is 1 whether the shift amount is obtained from the im5 field. From inspection of the diagram we see that bit 12 indicates the direction, with 1 for a left shift. Since one of the shift instructions has a zero opcode, thefor a left shift....
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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fe_sol - Name Solution Computer Architecture EE 4720 Final...

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