hw02_sol

hw02_sol - LSU EE 4720 Homework 2 Solution Due 17 September...

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Unformatted text preview: LSU EE 4720 Homework 2 Solution Due: 17 September 2010 Problem 1: Consider the execution of the code fragments below on the illustrated implementation. format&#13; immed&#13; IR&#13; Addr&#13; 25:21&#13; 20:16&#13; IR&#13; IF&#13; ID&#13; EX&#13; WB&#13; MEM&#13; IR&#13; IR&#13; rsv&#13; rtv&#13; IMM&#13; NPC&#13; ALU&#13; Addr&#13; Data&#13; Data&#13; Addr&#13; D In&#13; +4&#13; PC&#13; Mem&#13; Port&#13; Addr&#13; Data&#13; Out&#13; Addr&#13; Data&#13; In&#13; Mem&#13; Port&#13; Data&#13; Out&#13; rtv&#13; ALU&#13; MD&#13; dst&#13; dst&#13; dst&#13; Decode&#13; dest. reg&#13; =&#13; =0&#13; <0&#13; E&#13; Z&#13; N&#13; NPC&#13; • A value written to the register file can be read from the register file in the same cycle. (For example, if instruction A writes r1 in cycle x (meaning A is in WB in cycle x ) and instruction B is in ID in cycle x , then instruction B can read the value of r1 that A wrote.) • As one should expect, the illustrated implementation will execute the code correctly, as defined by MIPS-I, stalling and squashing as necessary. # SOLUTION Execution on the resolve-in-ME (illustrated) pipeline LOOP: # Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 lw r3, 0(r1) IF ID EX ME WB FIRST ITERATION add r4, r4, r3 IF ID ----> EX ME WB bne r1, r2 LOOP IF ----> ID EX ME WB addi r1, r1, 4 IF ID EX ME WB xor r7, r8, r3 IF IDx sw r4, 16(r5) IFx LOOP: # Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 lw r3, 0(r1) SECOND ITERATION IF ID EX ME WB add r4, r4, r3 IF ID ----> EX ME WB bne r1, r2 LOOP IF ----> ID EX ME WB addi r1, r1, 4 IF ID EX ME WB xor r7, r8, r3 IF IDx sw r4, 16(r5) IFx LOOP: # Cycles 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 lw r3, 0(r1) THIRD ITERATION IF ......
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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hw02_sol - LSU EE 4720 Homework 2 Solution Due 17 September...

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