hw03_sol(1)

hw03_sol(1) - LSU EE 4720 Homework 3 Solution Due: 19 April...

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Unformatted text preview: LSU EE 4720 Homework 3 Solution Due: 19 April 2010 Problem 1: The code below executes on the illustrated MIPS implementation. Assume that any reasonable bypasses needed for the FP operands are available, even though they are not shown in the illustration. A bypass is reasonable if it does not have a significant impact on clock frequency and if it does not use circuitry that can predict the future. format
 immed
 IR
 Addr
 25:21
 20:16
 IF
 EX
 WB
 MEM
 rsv
 rtv
 IMM
 NPC
 ALU
 Addr
 Data
 Data
 Addr
 D In
 +1
 PC
 Mem
 Port
 Addr
 Data
 Out
 Addr
 Data
 In
 Mem
 Port
 Data
 Out
 rtv
 ALU
 MD
 dst
 dst
 dst
 Decode
 dest. reg
 NPC
 Int Reg File
 FP Reg File
 fd
 fd
 WF
 Addr
 Data
 D In
 WE
 Addr
 Addr
 Data
 fsv
 ftv
 15:11
 20:16
 M6
 we
 we
 Decode
 dest. reg
 ID
 A4
 fd
 we
 fd
 we
 A3
 A2
 A1
 M3
 M4
 M5
 xw
 fd
 we
 xw
 fd
 we
 xw
 M2
 M
 1
 xw
 xw
 fd
 we
 uses FP mul
 uses FP add
 FP load
 Stall
 ID
 "0"
 "2"
 "1"
 30
 2
 "0"
 + 15:0
 29:0
 0
 1
 2
 1 # SOLUTION LOOP: # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 ldc1 f0, 0(r1) IF ID EX ME WF mul.d f2, f0, f4 IF ID -> M1 M2 M3 M4 M5 M6 WF add.d f6, f6, f2 IF -> ID -------------> A1 A2 A3 A4 WF bne r1, r2, LOOP IF -------------> ID EX ME WB addi r1, r1, 8 IF ID EX ME WB # Second Iteration Below LOOP: # 1 2 3 4 5 6 7 8...
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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hw03_sol(1) - LSU EE 4720 Homework 3 Solution Due: 19 April...

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