hw04(2)

# hw04(2) - LSU EE 4720 Homework 4 Due: 28 April 2010 Problem...

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LSU EE 4720 Homework 4 Due: 28 April 2010 Problem 1: A deeply pipelined MIPS implementation is constructed from our familiar Fve-stage pipeline by splitting IF , ID , and ME each into two stages, but leaving EX and WB as one stage. The total number of stages will be eight, call them F1 , F2 , D1 , D2 , EX , Y1 , Y2 , and WB . In this system branches are resolved at the end of D2 (rather than at the end of ID ). Assume that all reasonable bypass paths are present. ( a ) Provide a pipeline execution diagram of the code below for both the 5-stage and this new implementation, for enough iterations to compute the IPCs. LOOP: addi r2, r2, 4 lw r1, 0(r2) add r3, r3, r1 bne r5, r4 LOOP addi r5, r5, 1 ( b ) Suppose the 5-stage MIPS runs at 1 GHz. Choose a clock frequency for the 8-stage system for which the time to execute the code above is the same as for the 5-stage MIPS. ( c ) Consider two ways to make a 7-stage system from the 8-stage system. In method ID, the two ID stages ( D1 and D2 ) are merged back into one (or if you prefer, the ID stage was never split in the Frst place). In
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## This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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