hw04_sol(1)

hw04_sol(1) - LSU EE 4720 Homework 4 Solution Due: 28 April...

Info iconThis preview shows pages 1–2. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: LSU EE 4720 Homework 4 Solution Due: 28 April 2010 Problem 1: A deeply pipelined MIPS implementation is constructed from our familiar five-stage pipeline by splitting IF , ID , and ME each into two stages, but leaving EX and WB as one stage. The total number of stages will be eight, call them F1 , F2 , D1 , D2 , EX , Y1 , Y2 , and WB . In this system branches are resolved at the end of D2 (rather than at the end of ID ). Assume that all reasonable bypass paths are present. ( a ) Provide a pipeline execution diagram of the code below for both the 5-stage and this new implementation, for enough iterations to compute the IPCs. Solution appears below. Note that for the 8-stage system the second iteration, starting in cycle 9, starts with the processor in the same state as the third iteration, starting in cycle 18, and so the second iteration can be used to compute IPC. The execution rate is 5 18- 9 = 5 9 insn / cycle for the eight-stage system. By a similar argument the rate for the five-stage system is 5 12- 6 = 5 6 insn / cycle . # Solution # Eight-Stage Pipeline # LOOP: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 addi r2, r2, 4 F1 F2 D1 D2 EX Y1 Y2 WB lw r1, 0(r2) F1 F2 D1 D2 EX Y1 Y2 WB add r3, r3, r1 F1 F2 D1 D2 ----> EX Y1 Y2 WB bne r5, r4 LOOP F1 F2 D1 ----> D2 EX Y1 Y2 WB addi r5, r5, 1 F1 F2 ----> D1 D2 EX Y1 Y2 WB F1 ----> F2x F1x LOOP: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 addi r2, r2, 4 F1 F2 D1 D2 EX Y1 Y2 WB lw r1, 0(r2) F1 F2 D1 D2 EX Y1 Y2 WB add r3, r3, r1 F1 F2 D1 D2 ----> EX Y1 Y2.. bne r5, r4 LOOP F1 F2 D1 ----> D2 EX Y1.. addi r5, r5, 1 F1 F2 ----> D1 D2 EX.. F1 ----> F2x F1x LOOP: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 addi r2, r2, 4 F1 F2.. # Five-Stage Pipeline # LOOP: # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 addi r2, r2, 4 IF ID EX ME WB lw r1, 0(r2) IF ID EX ME WB add r3, r3, r1 IF ID -> EX ME WB bne r5, r4 LOOP IF -> ID EX ME WB addi r5, r5, 1 IF ID EX ME WB LOOP: # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 addi r2, r2, 4 IF ID EX ME WB lw r1, 0(r2) IF ID EX ME WB add r3, r3, r1 IF ID -> EX ME WB bne r5, r4 LOOP IF -> ID EX ME WB addi r5, r5, 1 IF ID EX ME WB LOOP: # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 addi r2, r2, 4 IF ID EX ME WB 1 (...
View Full Document

Page1 / 4

hw04_sol(1) - LSU EE 4720 Homework 4 Solution Due: 28 April...

This preview shows document pages 1 - 2. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online