hw04_sol

hw04_sol - LSU EE 4720 Homework 4 Solution Due: 4 September...

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Unformatted text preview: LSU EE 4720 Homework 4 Solution Due: 4 September 2010 Questions in this assignment are about VAX, an ISA that was mentioned in class but for which no details were given. Use the VAX-11 Architecture Reference Manual (Cover, 1982; text, 1980), which is linked to the course references page, as a reference for this assignment. (The VAX MACRO and Instruction Set Reference Manual can be used as a secondary reference; you may also use any other resources that you can find.) Chapter and section numbers in this assignment refer to the VAX-11 manual, not to the VAX MACRO manual. Problem 1: Compare the design goals for VAX as described in Section 1.1 to the design goals for SPARC as described in the SPARC Architecture Manual V8 Section 1.1 (also linked to the course references page). ( a ) List the design goals for each architecture that are considered defining elements of the respective ISA family (CISC and RISC). Explain whether the design goals in VAX and SPARC are mutually exclusive (meaning you can’t easily do both). The solution below is based on the EE 4720 ISA Families Overview notes. One VAX goals that is consistent with defining elements of CISC ISAs is “High bit efficiency,” which implies variable instruction size. Another “Systematic, elegant instruction set . . . ” can be interpreted to mean a large variety of immediate sizes and addressing modes, which is a CISC characteristic. (Of course, with no context “systematic, elegant” can mean anything.) If instead one interprets the “systematic, elegant” goal only to mean that there are few special-purpose registers and data types, then the goal is consistent with both CISC and RISC....
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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hw04_sol - LSU EE 4720 Homework 4 Solution Due: 4 September...

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