lsli06

lsli06 - 06-1 06-1 MIPS Implementation Material from...

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Unformatted text preview: 06-1 06-1 MIPS Implementation Material from Chapter 3 of H&P (for DLX). Material from Chapter 6 of P&H (for MIPS). Outline: (In this set.) Unpipelined DLX Implementation. (Diagram only.) Pipelined MIPS Implementations: Hardware, notation, hazards. Dependency Definitions. Data Hazards: Definitions, stalling, bypassing. Control Hazards: Squashing, one-cycle implementation. Outline: (Covered in class but not yet in set.) Operation of nonpipelined implementation, elegance and power of pipelined implementation. (See text.) Computation of CPI for program executing a loop. 06-1 EE 4720 Lecture Transparency. Formatted 9:29, 31 January 2011 from lsli06. 06-1 06-2 06-2 Unpipelined Implementation Instruction fetch Instruction decode/ register fetch Execute/ address calculation Memory access Write back B PC 4 ALU 16 32 Add Data memory Registers Sign extend Instruction memory M u x M u x M u x M u x Zero? Branch taken Cond NPC lmm ALU output IR A LMD FIGURE 3.1 The implementation of the DLX datapath allows every instruction to be executed in four or five clock cycles. 06-2 EE 4720 Lecture Transparency. Formatted 9:29, 31 January 2011 from lsli06. 06-2 06-3 06-3 Pipelined MIPS Implementation format&#13; immed&#13; IR&#13; Addr&#13; 25:21&#13; 20:16&#13; IR&#13; IF&#13; ID&#13; EX&#13; WB&#13; MEM&#13; IR&#13; IR&#13; rsv&#13; rtv&#13; IMM&#13; NPC&#13; ALU&#13; Addr&#13; Data&#13; Data&#13; Addr&#13; D In&#13; +4&#13; PC&#13; Mem&#13; Port&#13; Addr&#13; Data&#13; Out&#13; Addr&#13; Data&#13; In&#13; Mem&#13; Port&#13; Data&#13; Out&#13; rtv&#13; ALU&#13; MD&#13; dst&#13; dst&#13; dst&#13; Decode&#13; dest. reg&#13; =&#13; =0&#13; <0&#13; E&#13; Z&#13; N&#13; NPC&#13; Note: diagram omits connections for some instructions. 06-3 EE 4720 Lecture Transparency. Formatted 9:29, 31 January 2011 from lsli06. 06-3 06-4 06-4 Pipeline Details Pipeline Stages Divide pipeline into stages . Each stage occupied by at most one instruction. At any time, different stage can be occupied by different instructions. Stages given names: IF, ID, EX, ME, WB Sometimes ME written as MEM . 06-4 EE 4720 Lecture Transparency. Formatted 9:29, 31 January 2011 from lsli06. 06-4 06-5 06-5 Pipeline Latches Registers separating pipeline stages. Written at end of each cycle. To emphasize role, as bar separating stages. Registers named using pair of stage names and register name. For example, IF/ID.IR , ID/EX.IR , ID/EX.A (used in text, notes). if id ir , id ex ir , id ex rs val (used in Verilog code). 06-5 EE 4720 Lecture Transparency. Formatted 9:29, 31 January 2011 from lsli06. 06-5 06-6 06-6 Pipeline Execution Diagram Pipeline Execution Diagram Diagram showing the pipeline stages that instructions occupy as they execute....
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This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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lsli06 - 06-1 06-1 MIPS Implementation Material from...

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