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# mt(1) - Name Computer Architecture EE 4720 Midterm...

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Unformatted text preview: Name Computer Architecture EE 4720 Midterm Examination Friday, 26 March 2010, 10:40–11:30 CDT Alias Problem 1 (40 pts) Problem 2 (12 pts) Problem 3 (14 pts) Problem 4 (10 pts) Problem 5 (24 pts) Exam Total (100 pts) Good Luck! Problem 1: [40 pts] In the MIPS implementation below some wires are labeled with cycle numbers and values that will then be present. For example, c5:6 indicates that at cycle 5 the wire will hold a 6. Other wires are labeled just with cycle numbers, indicating that the wire is used at that cycle. If a value on any labeled wire is changed the code would execute incorrectly. Write a program consistent with these labels. All register numbers and immediate values can be determined. The first instruction address has been provided, show the addresses of the remaining four instructions . The third instruction is an addi , don’t forget to show its registers and immediates. If an instruction is a load or store, show all possible size and sign possibilities. For example, (lw,lh) format&#13; immed&#13; IR&#13; Addr&#13; 25:21&#13; 20:16&#13; IF&#13; ID&#13; EX&#13; WB&#13; ME&#13; rsv&#13; rtv&#13; IMM&#13; NPC&#13; ALU&#13; Addr&#13; Data&#13; Data&#13; Addr&#13; D In&#13; +1&#13; PC&#13; Mem&#13; Port&#13; Addr&#13; Data&#13; Out&#13; Addr&#13; Data&#13; In&#13; Mem&#13; Port&#13; Data&#13; Out&#13; rtv&#13; ALU&#13; MD&#13; dst&#13; dst&#13; dst&#13; Decode&#13; dest. reg&#13; NPC&#13; =&#13; 30&#13; 2&#13; 2’b0&#13; + 15:0&#13; 25:0&#13; 29:26&#13; 29:0&#13; 0&#13;1&#13; 15:0&#13; C2:2&#13; C3:2&#13; C5:2&#13; C1&#13; C5:6&#13; C3:1&#13; C5:0&#13; C3:8&#13; C5:3&#13; C6&#13; C5&#13; C3:16&#13; C5&#13;...
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## This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

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mt(1) - Name Computer Architecture EE 4720 Midterm...

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