mt_sol(1)

mt_sol(1) - Name Solution Computer Architecture EE 4720...

Info iconThis preview shows pages 1–4. Sign up to view the full content.

View Full Document Right Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon

Info iconThis preview has intentionally blurred sections. Sign up to view the full version.

View Full DocumentRight Arrow Icon
This is the end of the preview. Sign up to access the rest of the document.

Unformatted text preview: Name Solution Computer Architecture EE 4720 Midterm Examination Friday, 26 March 2010, 10:40–11:30 CDT Alias Buffer Size + 1 Problem 1 (40 pts) Problem 2 (12 pts) Problem 3 (14 pts) Problem 4 (10 pts) Problem 5 (24 pts) Exam Total (100 pts) Good Luck! Problem 1: [40 pts] In the MIPS implementation below some wires are labeled with cycle numbers and values that will then be present. For example, c5:6 indicates that at cycle 5 the wire will hold a 6. Other wires are labeled just with cycle numbers, indicating that the wire is used at that cycle. If a value on any labeled wire is changed the code would execute incorrectly. Write a program consistent with these labels. checked All register numbers and immediate values can be determined. checked The first instruction address has been provided, show the addresses of the remaining four instructions . checked The third instruction is an addi , don’t forget to show its registers and immediates. checked If an instruction is a load or store, show all possible size and sign possibilities. For example, (lw,lh) format
 immed
 IR
 Addr
 25:21
 20:16
 IF
 ID
 EX
 WB
 ME
 rsv
 rtv
 IMM
 NPC
 ALU
 Addr
 Data
 Data
 Addr
 D In
 +1
 PC
 Mem
 Port
 Addr
 Data
 Out
 Addr
 Data
 In
 Mem
 Port
 Data
 Out
 rtv
 ALU
 MD
 dst
 dst
 dst
 Decode
 dest. reg
 NPC
 =
 30
 2
 2’b0
 + 15:0
 25:0
 29:26
 29:0
 0
1
 15:0
 C2:2
 C3:2
 C5:2
 C1
 C5:6
 C3:1
 C5:0
 C3:8
 C5:3
 C6
 C5
 C3:16
 C5
 C5:0xabcd1234
 C0: 0001 0001 1001 0100 0000 0000 0010 0000
 # SOLUTION # # Cycle 1 2 3 4 5 6 7 8 0x1000 beq r12, r20 TA IF ID EX ME WB 0x1004 lw r8, 16(r2) IF ID EX ME WB TA:0x1084 addi r3, r2, 1 IF ID EX ME WB 0x1088 sb r3, 0(r3) IF ID EX ME WB 0x108c sh (or sb) r3, 6(r2) IF ID EX ME WB # Cycle 1 2 3 4 5 6 7 8 Easy Stuff: The destination for second instruction, r8 , and the third instruction, r3 , can be read off the ID/EX.dst and EX/ME.dst pipeline latches. Similarly, the first source register of several instructions can be read directly at the input to the register file in ID . Three immediate values are directly provided on both sides of the ID/EX.IMM pipeline latch. If this doesn’t seem obvious within five minutes, please please please see the Statically Scheduled System Study Guide for tips and other sample problems, also consider asking for help. Don’t bother reading the next paragraphs until everything above is easy. 2 Dependencies: The use of bypass paths shown by the two C5 bubbles and C6 bubble in EX reveals three dependencies. For example, the upper C5 means that the rs source of the fourth instruction is the same as the destination of the third (otherwise the bypass path would not be used). In this particular problem the result of the third instruction is bypassed to three places, two inthe bypass path would not be used)....
View Full Document

This note was uploaded on 12/11/2011 for the course EE 4720 taught by Professor Staff during the Fall '08 term at LSU.

Page1 / 11

mt_sol(1) - Name Solution Computer Architecture EE 4720...

This preview shows document pages 1 - 4. Sign up to view the full document.

View Full Document Right Arrow Icon
Ask a homework question - tutors are online