cpe631bpred - CPE 631: Branch Prediction Electrical and...

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CPE 631: Branch Prediction Electrical and Computer Engineering University of Alabama in Huntsville Aleksandar Milenkovic, milenka@ece.uah.edu http://www.ece.uah.edu/~milenka
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2 AM L a CA S A The Case for Branch Prediction Dynamic scheduling increases the amount of ILP => control dependence becomes the limiting factor Multiple issue processors Branches will arrive up to N times faster in an n-issue processor Amdahl’s Law => relative impact of the control stalls will be larger with the lower potential CPI in an n-issue processor What have we done? Static schemes for dealing with branches – compiler optimizes the the branch behavior by scheduling it at compile time
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3 AM L a CA S A 7 Branch Prediction Schemes 1-bit Branch-Prediction Buffer 2-bit Branch-Prediction Buffer Correlating Branch Prediction Buffer Tournament Branch Predictor Branch Target Buffer Integrated Instruction Fetch Units Return Address Predictors
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4 AM L a CA S A Basic Branch Prediction (1) Performance = ƒ(accuracy, cost of misprediction) Branch History Table : a small table of 1-bit values indexed by the lower bits of PC address Says whether or not branch taken last time Useful only to reduce branch delay when it is longer than the time to compute the possible target PC No address check – BHT has no address tags, so the prediction bit may have been put by another branch that has the same low-order bits Prediction is a hint, assumed to be correct – fetching begins in the predicted direction; if it turns out to be wrong, the prediction bit is inverted and stored back
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5 AM L a CA S A Basic Branch Prediction (2) Problem: in a loop, 1-bit BHT will cause 2 mispredictions (avg is 9 iterations before exit): End of loop case, when it exits instead of looping as before First time through loop on next time through code, when it predicts exit instead of looping Only 80% accuracy even if loop 90% of the time Ideally for highly regular branches, the accuracy of predictor = taken branch frequency Solution: use two-bit prediction schemes
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6 AM L a CA S A 2-bit Scheme States in a two-bit prediction scheme Red : stop, not taken Green : go, taken Adds hysteresis to decision making process NT T T Predict Taken Predict Not Taken Predict Taken Predict Not Taken T NT T NT NT
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7 AM L a CA S A BHT Implementation 1) Small, special “cache” accessed with the instruction address during the IF pipe stage 2) Pair of bits attached to each block in the instruction cache and fetched with the instruction How many branches per instruction? Complexity? Instruction is decoded as branch, and branch is predicted as taken => fetch from the target as soon as the PC is known Note: Does this scheme help for simple MIPS?
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8 AM L a CA S A BHT Performance Prediction accuracy of 2-bit predictor with 4096 entries is ranging from over 99% to 82% or misprediction rate of 1% to 18% Real impact on performance:
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cpe631bpred - CPE 631: Branch Prediction Electrical and...

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